Adaptive gate driver with negative temperature coefficient (NTC) resistor
An adaptive gate drive circuit for an insulated gate bridge transistor, IGBT, based semiconductor switch provides a gate resistance device for reducing timing delays and switching losses associated with an increase in switch junction temperature. The gate resistance device is disposed close to the switch junction and including a negative temperature coefficient, NTC, thermistor and linear gate resistor connected in parallel. When the thermistor senses an increase in the junction temperature of the semiconductor switch, gate resistance via the linear gate resistor is reduced to bring the junction temperature back to thermal equilibrium with minimal delay, allowing the semiconductor switch to switch faster and reducing associated switching losses.
1 . A gate drive circuit for a semiconductor device, comprising:
at least one semiconductor switch configured to supply a power to the semiconductor device in response to a control signal received from a control switch, the at least one semiconductor switch associated with:
a radiated emissions limit;
and
a junction temperature;
wherein a gate drive voltage associated with the power is one of:
a positive voltage corresponding to an on state, the on state associated with at least one of a turn-on switching timing or a turn-on switching loss;
or
a non-positive voltage corresponding to an off state, the off state associated with at least one of a turn-off switching timing or a turn-off switching loss;
and
a gate resistance device serially connected between the control switch and the at least one semiconductor switch, the gate resistance device thermally coupled to the at least one semiconductor switch, the gate resistance device comprising a negative temperature coefficient (NTC) thermistor and a gate resistor connected in parallel;
wherein the gate resistance device is configured to:
sense the junction temperature associated with at least one of the on state or the off state based on a relationship between the junction temperature and a resistance of the NTC thermistor;
and
in response to a change in the junction temperature, adjust one or more of the associated turn-on or turn-off switching timing or the associated turn-on or turn-off switching loss by adjusting a gate resistance of the gate resistor based on an inverse linear relationship between the junction temperature and a resistance of the gate resistance device.
2 . The gate drive circuit of claim 1 , wherein the gate resistance device is configured to reduce the gate resistance until the junction temperature is reduced below the threshold level.
3 . The gate drive circuit of claim 1 , wherein the gate resistance device is configured to increase the gate resistance based on a reduced current load associated with the gate drive voltage.
4 . The gate drive circuit of claim 1 , wherein the gate resistance device is configured to increase the gate resistance based on a reduction in the sensed junction temperature.
5 . The gate drive circuit of claim 1 , wherein the gate resistor is associated with:
a minimum gate resistance corresponding to the radiated emissions limit;
and
a maximum gate resistance based on a power capacity of the semiconductor switch.
6 . The gate drive circuit of claim 1 , wherein the at least one semiconductor switch includes at least one insulated gate bipolar transistor, IGBT.
7 . The gate drive circuit of claim 1 , wherein:
the semiconductor device is a system-on-a-chip, SoC;
and
the at least one semiconductor switch and the gate resistance device includes at least one surface-mounted device, SMD.
8 . The gate drive circuit of claim 1 , wherein the turn-on switching timing includes at least one of:
a turn-on delay associated with the on state;
a rise time associated with the on state;
or
a charging time associated with the on state.
9 . The gate drive circuit of claim 1 , wherein the turn-off switching timing includes at least one of:
a turn-off delay associated with the off state;
a fall time associated with the off state;
and
a discharging time associated with the off state.
10 . A method for optimal switching of a semiconductor device, the method comprising:
serially connecting a gate resistance device between a semiconductor switch of the semiconductor device and a control switch of the semiconductor device,
the semiconductor switch configured for supplying a power to the semiconductor device in response to a control signal received from the control switch, the semiconductor switch associated with a radiated emissions limit and a junction temperature, a gate drive voltage associated with the power corresponding to at least one of an on state or an off state, the on state associated with a turn-on switching timing and a turn-on switching loss, the off state associated with a turn-off switching timing and a turn-off switching loss;
and
the gate resistance device thermally coupled to the semiconductor switch and comprising a negative temperature coefficient (NTC) thermistor and a gate resistor connected in parallel;
sensing, via the NTC thermistor, the junction temperature associated with at least one of the on state or the off state based on a relationship between the junction temperature and a resistance of the NTC thermistor;
and
in response to a change in the junction temperature, adjusting one or more of the associated turn-on or turn-off switching timing or the associated turn-on or turn-off switching loss by adjusting a gate resistance of the gate resistor based on an inverse linear relationship between the junction temperature and a resistance of the gate resistance device.
11 . The method of claim 10 , wherein in response to a change in the junction temperature, adjusting a gate resistance of the gate resistor, includes:
when the junction temperature meets or exceeds a threshold level, reducing the gate resistance until the junction temperature is reduced below the threshold level.
12 . The method of claim 10 , further comprising:
increasing, via the gate resistance device, the gate resistance based on a reduced current load associated with the gate drive voltage.
13 . The method of claim 10 , further comprising:
increasing, via the gate resistance device, the gate resistance based on a reduction in the sensed junction temperature.
14 . The method of claim 10 , wherein the gate resistor is associated with:
a minimum gate resistance corresponding to the radiated emissions limit;
and
a maximum gate resistance based on a power capacity of the semiconductor switch.
15 . The method of claim 10 , wherein the semiconductor switch is an insulated gate bipolar transistor, IGBT.
16 . The method of claim 10 , wherein:
the semiconductor device is a system-on-a-chip, SoC;
and
the at least one semiconductor switch and the gate resistance device includes at least one surface-mounted device, SMD.
17 . The method of claim 10 , wherein the turn-on switching timing includes at least one of:
a turn-on delay associated with the on state;
a rise time associated with the on state;
or
a charging time associated with the on state.
18 . The method of claim 10 , wherein the turn-off switching timing includes at least one of:
a turn-off delay associated with the off state;
a fall time associated with the off state;
or
a discharging time associated with the off state.