IP Library › Granted Patent US 12706601
Granted Patent B2
US 12706601 · App. 18/428,672 · Granted Aug 11, 2026

Switch-based voltage translator

Inventors: Ajith Kumar Narayanasetty (Bangalore, IN); Sahil Garg (Bangalore, IN)
Assignee: TEXAS INSTRUMENTS INCORPORATED
H03K17/161
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Quick Facts
Patent No.
US 12706601
App. No.
18/428,672
Granted
Aug 11, 2026
Kind
B2
Abstract

In an example, a system includes a first transistor having a control terminal, a first terminal, and a second terminal. The system also includes a resistor having first and second terminals, the first terminal of the resistor coupled to the control terminal of the first transistor, and the second terminal of the resistor coupled to a first voltage terminal. The system includes a second transistor having a control terminal, a first terminal, and a second terminal, where the first terminal of the second transistor is coupled to the control terminal of the first transistor and to the first terminal of the resistor, and the second terminal of the second transistor is coupled to the control terminal of the second transistor.

Claims (48)

1 . A voltage translation circuit comprising:

first and second channel terminals;

first and second supply terminals;

a first transistor having a control terminal, a first terminal coupled to the first channel terminal, and a second terminal coupled to the second channel terminal;

a resistor having first and second terminals, the first terminal of the resistor coupled to the control terminal of the first transistor, and the second terminal of the resistor coupled to the first supply terminal;

a second transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal of the second transistor is coupled to the control terminal of the first transistor and to the first terminal of the resistor, and the second terminal of the second transistor is coupled to the control terminal of the second transistor, and to the first supply terminal; and

a third transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal of the third transistor is coupled to the control terminal of the first transistor and to the first terminal of the second transistor, and wherein the control terminal of the third transistor is coupled to the second terminal of the third transistor and to the second supply terminal.

2 . The voltage translation circuit of claim 1 , further comprising:

a first resistor having first and second terminals, the first terminal of the first resistor coupled to the first terminal of the first transistor, and the second terminal of the first resistor coupled to the first supply terminal; and

a second resistor having first and second terminals, the first terminal of the second resistor coupled to the second terminal of the first transistor, and the second terminal of the second resistor coupled to a third supply terminal.

3 . The voltage translation circuit of claim 1 , wherein the first transistor is at least twice a size of the second transistor.

4 . The voltage translation circuit of claim 1 , wherein the first transistor has a threshold voltage below 0.75 volts.

5 . The voltage translation circuit of claim 1 , wherein the voltage translation circuit is integrated in an integrated circuit.

6 . The voltage translation circuit of claim 1 , further comprising:

a first resistor coupled between the first channel terminal and the first supply terminal; and

a second resistor coupled between the second channel terminal and a third supply terminal.

7 . The voltage translation circuit of claim 2 , wherein the first supply terminal is configured to supply a first voltage, the second supply terminal is a ground terminal, and the third supply terminal is configured to supply a second voltage that is different than the first voltage.

8 . The voltage translation circuit of claim 7 , wherein the first voltage is lower than 0.75 volts, and the second voltage is higher than 0.75 volts.

9 . A circuit comprising:

a first transistor having a control terminal, a first terminal, and a second terminal;

a resistor having first and second terminals, the first terminal of the resistor coupled to the control terminal of the first transistor, and the second terminal of the resistor coupled to a first voltage terminal;

a second transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal of the second transistor is coupled to the control terminal of the first transistor and to the resistor, and the second terminal of the second transistor is coupled to the control terminal of the second transistor; and

a third transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal of the third transistor is coupled to the control terminal of the first transistor and to the first terminal of the second transistor, and wherein the control terminal of the third transistor is coupled to the second terminal of the third transistor and to a second voltage terminal.

10 . The circuit of claim 9 , further comprising:

a first pullup resistor having first and second terminals, the first terminal of the first pullup resistor coupled to the first terminal of the first transistor, and the second terminal of the first pullup resistor configured to receive a first voltage from the first voltage terminal; and

a second pullup resistor having first and second terminals, the first terminal of the second pullup resistor coupled to the second terminal of the first transistor, and the second terminal of the second pullup resistor configured to receive a second voltage from a third voltage terminal, wherein the first voltage is different than the second voltage.

11 . The circuit of claim 10 , wherein the first voltage from the first voltage terminal is less than 0.75 volts, and the second voltage from the third voltage terminal is higher than 0.75 volts.

12 . The circuit of claim 9 , wherein the control terminal of the second transistor is coupled to a ground terminal.

13 . The circuit of claim 9 , wherein the first transistor is at least twice a size of the second transistor.

14 . The circuit of claim 9 , wherein the first transistor has a threshold voltage below 0.75 volts.

15 . The circuit of claim 9 , further comprising:

a first device having a supply terminal coupled to the first voltage terminal, and a first terminal coupled to the first terminal of the first transistor; and

a second device having a supply terminal coupled to a third voltage terminal, and a first terminal coupled to the second terminal of the first transistor.

16 . A circuit comprising:

a first transistor having a control terminal, a first terminal, and a second terminal, the first transistor configured to translate a voltage from a first voltage domain to a second voltage domain;

a resistor having first and second terminals, the first terminal of the resistor coupled to the control terminal of the first transistor, and the second terminal of the resistor coupled to a first voltage terminal configured to provide a first voltage, the resistor configured to bias the control terminal of the first transistor and to produce a voltage drop at the control terminal of the first transistor responsive to a leakage current in the first transistor;

a second transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal of the second transistor is coupled to the control terminal of the first transistor and to the resistor, the second terminal of the second transistor is coupled to the control terminal of the second transistor, and the second transistor is configured to draw a leakage current responsive to the leakage current in the first transistor; and

a third transistor having a control terminal, a first terminal, and a second terminal, wherein the first terminal of the third transistor is coupled to the control terminal of the first transistor and to the first terminal of the second transistor, wherein the control terminal of the third transistor is coupled to the second terminal of the third transistor and to a second voltage terminal, and wherein the third transistor is configured to hold a voltage at the control terminal of the first transistor above a threshold responsive to the leakage current in the first transistor.

17 . The circuit of claim 16 , further comprising:

a first pullup resistor having first and second terminals, the first terminal of the first pullup resistor coupled to the first terminal of the first transistor, and the second terminal of the first pullup resistor coupled to the first voltage terminal, the first pullup resistor configured to pull up a voltage at the first terminal of the first transistor for voltage translation; and

a second pullup resistor having first and second terminals, the first terminal of the second pullup resistor coupled to the second terminal of the first transistor, and the second terminal of the second pullup resistor coupled to a third voltage terminal configured to provide a second voltage, wherein the first voltage is different than the second voltage, and wherein the second pullup resistor is configured to pull up a voltage at the second terminal of the first transistor for voltage translation.

18 . The circuit of claim 17 , wherein the first pullup resistor is configured to receive a first voltage from the first voltage terminal less than 0.75 volts.

19 . The circuit of claim 18 , wherein the second pullup resistor is configured to receive a second voltage from the second voltage terminal higher than 0.75 volts.

20 . The circuit of claim 16 , wherein the control terminal of the second transistor is coupled to a ground terminal.

21 . The circuit of claim 16 , wherein the first transistor and the second transistor each have a threshold voltage below 0.75 volts.

22 . The circuit of claim 16 , further comprising:

a first device configured to operate in the first voltage domain, the first device coupled to the first terminal of the first transistor; and

a second device configured to operate in the second voltage domain, the second device coupled to the second terminal of the first transistor.