IP Library › Granted Patent US 12,706,602

Granted Patent B2

US 12,706,602 · App. 18/811,418 · Granted Aug 11, 2026

Methods and apparatus to control a slew rate of driver circuitry

Inventors: Qunying Li (Allen, TX); Lester Boampong (Dallas, TX); Lawrence Cotton (Allen, TX)

Assignee: TEXAS INSTRUMENTS INCORPORATED

H03K17/163 H03K17/08104 H03K2217/0063 H03K2217/0072

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 12,706,602
App. No.: 18/811,418
Granted: Aug 11, 2026
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

An example apparatus includes: current source circuitry having a first terminal and a second terminal; current sink circuitry having a first terminal and a second terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the first terminal of the current source circuitry; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the current sink circuitry; and a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the second terminal of the first transistor and the second terminal of the second transistor, the second terminal of the capacitor coupled to the second terminal of the current source circuitry, and the second terminal of the current sink circuitry.

Claims (98)

1 . An apparatus comprising:

current source circuitry having a first terminal and a second terminal;

current sink circuitry having a first terminal and a second terminal;

a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the first terminal of the current source circuitry;

a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the current sink circuitry;

a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the second terminal of the first transistor and the second terminal of the second transistor, the second terminal of the capacitor coupled to the second terminal of the current source circuitry, the second terminal of the current sink circuitry, the control terminal of the first transistor, and the control terminal of the second transistor; and

wherein the first and second transistors are configured to produce a shoot-through current during switching of the first and second transistors.

2 . The apparatus of claim 1 , further comprising:

a third transistor having a first terminal and a second terminal; and

a fourth transistor having a first terminal and a second terminal, the first terminal of the fourth transistor coupled to the second terminal of the current source circuitry, the control terminal of the first transistor, and the first terminal of the third transistor, the second terminal of the fourth transistor coupled to the second terminal of the current sink circuitry, the control terminal of the second transistor, the second terminal of the third transistor, and the second terminal of the capacitor.

3 . The apparatus of claim 2 , wherein the capacitor is a first capacitor, the third transistor further having a control terminal, and the apparatus further comprising:

a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor coupled to the second terminal of the first transistor, the second terminal of the second transistor, and the first terminal of the first transistor; and

a fifth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor coupled to the first terminal of the current source circuitry and the first terminal of the first transistor, the second terminal of the fifth transistor is coupled to the second terminal of the current source circuitry, the control terminal of the first transistor, the first terminal of the third transistor, the first terminal of the fourth transistor, and the second terminal of the second capacitor, the control terminal of the fifth transistor coupled to the control terminal of the third transistor.

4 . The apparatus of claim 2 , wherein the third transistor further having a control terminal, and the apparatus further comprising:

a Zener diode having a first terminal and a second terminal; and

a fifth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor coupled to the first terminal of the current sink circuitry, the first terminal of the second transistor, and the first terminal of the Zener diode, the second terminal of the fifth transistor coupled to the second terminal of the current sink circuitry, the control terminal of the second transistor, the second terminal of the capacitor, and the second terminal of the Zener diode, the control terminal of the fifth transistor coupled to the control terminal of the third transistor.

5 . The apparatus of claim 1 , further comprising:

a first resistor having a first terminal and a second terminal;

a third transistor having a first terminal and a control terminal, the first terminal of the third transistor is coupled to the first terminal of the current source circuitry, the first terminal of the first transistor, and the first terminal of the first resistor, the control terminal of the third transistor coupled to the second terminal of the first resistor;

a second resistor having a first terminal and a second terminal; and

a fourth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor coupled to the second terminal of the first transistor, the first terminal of the capacitor, and the first terminal of the second resistor, the second terminal of the fourth transistor coupled to the second terminal of the second transistor, the control terminal of the fourth transistor coupled to the second terminal of the second resistor.

6 . The apparatus of claim 5 , further comprising:

clamp circuitry having a first terminal and a second terminal, the first terminal of the clamp circuitry coupled to the first terminal of the current sink circuitry and the first terminal of the second transistor;

a third resistor having a first terminal and a second terminal, the first terminal of the third resistor coupled to the second terminal of the fifth transistor;

an inverter having a first terminal and a second terminal, the first terminal of the inverter coupled to the second terminal of the third resistor; and

a sixth transistor having a first terminal and a control terminal, the first terminal of the sixth transistor coupled to the second terminal of the first resistor and the control terminal of the third transistor, the control terminal of the sixth transistor coupled to the second terminal of the inverter.

7 . The apparatus of claim 5 , further comprising:

charge pump circuitry having a first terminal and a second terminal, the first terminal of the charge pump circuitry coupled to the second terminal of the second resistor and the control terminal of the fourth transistor;

a third resistor having a first terminal and a second terminal, the first terminal of the third resistor coupled to the second terminal of the first transistor, the first terminal of the fourth transistor, and the first terminal of the capacitor;

a fifth transistor having a first terminal and a control terminal, the control terminal of the fifth transistor coupled to the second terminal of the third resistor;

a sixth transistor having a first terminal and a control terminal, the control terminal of the sixth transistor coupled to the first terminal of the fifth transistor; and

an inverter having a first terminal and a second terminal, the first terminal of the inverter coupled to the first terminal of the sixth transistor, the second terminal of the inverter coupled to the second terminal of the charge pump circuitry.

8 . An apparatus comprising:

a first transistor having a first terminal and a control terminal;

a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor and the control terminal of the first transistor;

a first capacitor having a first terminal and a second terminal;

a second capacitor having a first terminal and a second terminal;

a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the second terminal of the second transistor, the first terminal of the first capacitor, and the first terminal of the second capacitor, and the control terminal of the third transistor;

a fourth transistor having a first terminal and a control terminal, the first terminal of the fourth transistor coupled to the second terminal of the third transistor;

a fifth transistor having a first terminal and a second terminal; and

a sixth transistor having a first terminal and a second terminal, the first terminal of the sixth transistor coupled to the control terminal of the second transistor, the second terminal of the first capacitor, and the first terminal of the fifth transistor, the second terminal of the sixth transistor coupled to the second terminal of the second capacitor, the control terminal of the fourth transistor, and the second terminal of the fifth transistor.

9 . The apparatus of claim 8 , wherein the fourth transistor further has a second terminal, and the apparatus further comprising:

first current source circuitry having a first terminal and a second terminal, the first terminal of the first current source circuitry coupled to the first terminal of the first transistor and the first terminal of the second transistor, the second terminal of the first current source circuitry coupled to the control terminal of the second transistor, the second terminal of the first capacitor, the first terminal of the fifth transistor, and the first terminal of the sixth transistor; and

second current source circuitry having a first terminal and a second terminal, the first terminal of the second current source circuitry coupled to the second terminal of the second capacitor, the control terminal of the fourth transistor, the second terminal of the fifth transistor, and the second terminal of the sixth transistor, the second terminal of the second current source circuitry coupled to the second terminal of the fourth transistor.

10 . The apparatus of claim 8 , wherein the fourth transistor further has a second terminal, the fifth transistor further has a control terminal, and the apparatus further comprising:

a seventh transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh transistor coupled to the first terminal of the first transistor and the first terminal of the second transistor, the second terminal of the seventh transistor coupled to the control terminal of the second transistor, the second terminal of the first capacitor, the first terminal of the fifth transistor, and the first terminal of the sixth transistor; and

an eighth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the eighth transistor coupled to the second terminal of the second capacitor, the control terminal of the fourth transistor, the second terminal of the fifth transistor, and the second terminal of the sixth transistor, the second terminal of the eighth transistor coupled to the second terminal of the fourth transistor, the control terminal of the eighth transistor coupled to the control terminal of the fifth transistor and the control terminal of the seventh transistor.

11 . The apparatus of claim 8 , further comprising:

a first resistor having a first terminal and a second terminal;

clamp circuitry having a terminal;

a seventh transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh transistor coupled to the first terminal of the first transistor, the first terminal of the second transistor, and the first terminal of the first resistor, the control terminal of the seventh transistor coupled to the terminal of the clamp circuitry;

a second resistor having a first terminal and a second terminal, the first terminal of the second resistor coupled to the second terminal of the seventh transistor;

an inverter having a first terminal and a second terminal, the first terminal of the inverter coupled to the second terminal of the second resistor; and

an eighth transistor having a first terminal and a control terminal, the first terminal of the eighth transistor coupled to the second terminal of the first resistor and the control terminal of the first transistor, the control terminal of the eighth transistor coupled to the second terminal of the inverter.

12 . The apparatus of claim 11 , wherein the fifth transistor further has a control terminal, the sixth transistor further has a control terminal, the inverter is a first inverter, and the apparatus further comprising a second inverter having a first terminal and a second terminal, the first terminal of the second inverter coupled to the second terminal of the first inverter, the control terminal of the sixth transistor, and the control terminal of the eighth transistor, the second terminal of the second inverter coupled to the control terminal of the fifth transistor.

13 . The apparatus of claim 8 , further comprising:

a first resistor having a first terminal and a second terminal;

charge pump circuitry having a first terminal and a second terminal, the first terminal of the charge pump circuitry coupled to the second terminal of the first resistor and the control terminal of the third transistor;

a second resistor having a first terminal and a second terminal, the first terminal of the second resistor coupled to the second terminal of the second transistor, the first terminal of the first capacitor, the first terminal of the second capacitor, the first terminal of the third transistor, and the first terminal of the first resistor;

a seventh transistor having a first terminal and a control terminal, the control terminal of the seventh transistor coupled to the second terminal of the second resistor;

an eighth transistor having a first terminal and a control terminal, the control terminal of the eighth transistor coupled to the first terminal of the seventh transistor; and

an inverter having a first terminal and a second terminal, the first terminal of the inverter coupled to the first terminal of the eighth transistor, the second terminal of the inverter coupled to the second terminal of the charge pump circuitry.

14 . The apparatus of claim 13 , wherein the fifth transistor further has a control terminal, the sixth transistor further has a control terminal, the inverter is a first inverter, and the apparatus further comprising a second inverter having a first terminal and a second terminal, the first terminal of the second inverter coupled to the control terminal of the sixth transistor, the second terminal of the first inverter, and the second terminal of the charge pump circuitry, the second terminal of the second inverter coupled to the control terminal of the fifth transistor.

15 . An apparatus comprising:

a first transistor having a first terminal and a control terminal;

a second transistor having a first terminal and a control terminal;

a first capacitor having a first terminal and a second terminal;

a second capacitor having a first terminal and a second terminal, the first terminal of the second capacitor coupled to the first terminal of the first transistor, the first terminal of the second transistor, and the first terminal of the first capacitor;

first current source circuitry having a terminal;

second current source circuitry having a terminal;

a third transistor having a first terminal and a second terminal;

a fourth transistor having a first terminal and a second terminal, the first terminal of the fourth transistor coupled to the control terminal of the first transistor, the second terminal of the first capacitor, the terminal of the first current source circuitry, and the first terminal of the third transistor, the second terminal of the fourth transistor coupled to the control terminal of the second transistor, the second terminal of the second capacitor, the terminal of the second current source circuitry, and the second terminal of the third transistor; and

wherein the first and second transistors are configured to produce a shoot-through current during switching of the first and second transistors.

16 . The apparatus of claim 15 , wherein the first transistor further has a second terminal, the terminal of the first current source circuitry is a first terminal, the first current source circuitry further having a second terminal, the third transistor further has a control terminal, and the apparatus further comprising:

a Zener diode having a first terminal and a second terminal; and

a fifth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor coupled to the second terminal of the first current source circuitry and the second terminal of the first transistor, and the first terminal of the Zener diode, the second terminal of the fifth transistor coupled to the control terminal of the first transistor, the second terminal of the first capacitor, the first terminal of the first current source circuitry, the first terminal of the third transistor, the first terminal of the fourth transistor, and the second terminal of the Zener diode, the control terminal of the fifth transistor coupled to the control terminal of the third transistor.

17 . The apparatus of claim 15 , wherein the second transistor further has a second terminal, the terminal of the second current source circuitry is a first terminal, the second current source circuitry further having a second terminal, the third transistor further has a control terminal, and the apparatus further comprising:

a Zener diode having a first terminal and a second terminal; and

a fifth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor coupled to the second terminal of the second current source circuitry and the second terminal of the second transistor, and the first terminal of the Zener diode, the second terminal of the fifth transistor coupled to the control terminal of the second transistor, the second terminal of the second capacitor, the first terminal of the second current source circuitry, the second terminal of the third transistor, the second terminal of the fourth transistor, and the second terminal of the Zener diode, the control terminal of the fifth transistor coupled to the control terminal of the third transistor.

18 . The apparatus of claim 15 , wherein the first transistor further has a second terminal, the terminal of the first current source circuitry is a first terminal, the first current source circuitry further has a second terminal, and the apparatus further comprising:

a resistor having a first terminal and a second terminal;

a fifth transistor having a first terminal and a control terminal, the first terminal of the fifth transistor coupled to the second terminal of the first transistor, the second terminal of the first current source circuitry, and the first terminal of the resistor, the control terminal of the fifth transistor coupled to the second terminal of the resistor; and

a sixth transistor having a first terminal and a second terminal, the first terminal of the sixth transistor coupled to the first terminal of the first transistor, the first terminal of the first capacitor, and the first terminal of the second capacitor, the second terminal of the sixth transistor coupled to the first terminal of the second transistor.

19 . The apparatus of claim 18 , wherein the resistor is a first resistor, further comprising:

clamp circuitry having a terminal;

a seventh transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the seventh transistor coupled to the second terminal of the first transistor, the first terminal of the fifth transistor, and the first terminal of the first resistor, the control terminal of the seventh transistor coupled to the terminal of the clamp circuitry;

a second resistor having a first terminal and a second terminal, the first terminal of the second resistor coupled to the second terminal of the seventh transistor;

an inverter having a first terminal and a second terminal, the first terminal of the inverter coupled to the second terminal of the second resistor; and

an eighth transistor having a first terminal and a control terminal, the first terminal of the eighth transistor coupled to the second terminal of the first resistor and the control terminal of the fifth transistor, the control terminal of the eighth transistor coupled to the second terminal of the inverter.

20 . The apparatus of claim 18 , wherein the resistor is a first resistor, and the apparatus is further comprising:

a second resistor having a first terminal and a second terminal;

a third resistor having a first terminal and a second terminal, the first terminal of the third resistor coupled to the first terminal of the first transistor, the first terminal of the first capacitor, the first terminal of the second capacitor, the first terminal of the sixth transistor, and the first terminal of the second resistor;

a seventh transistor having a first terminal and a control terminal, the control terminal of the seventh transistor coupled to the second terminal of the third resistor;

an eighth transistor having a first terminal and a control terminal, the control terminal of the eighth transistor coupled to the first terminal of the seventh transistor; and

21 . The apparatus of claim 1 , wherein the shoot-through current during switching of the first and second transistors is to reduce variation in a switching time of the first and second transistors.