Triple module redundant solid state power switch
Herein presented are systems and methods for majority-vote, single fault tolerant switching of a switch using an electrical circuit that involves power transistors that carry relatively large electrical currents through the switch. The number of power transistors in the circuit of a majority-vote, single fault tolerant power switch may be reduced to four, thus saving circuit board space and producing relatively less heat. This may be done by avoiding the use of a third electrical branch that is generally used for triple module redundant power switches. In cases where a power transistor is relatively large and produces a relatively large amount of heat, reducing the number of this type of circuit component in a switch circuit may provide benefits such as reduced circuit board footprint and reduced heat generation.
1 . An electrical circuit for a majority-vote, single fault tolerant power switch, the electrical circuit comprising:
a power source input node to provide voltage and current;
a load output node to conditionally provide the voltage and the current to a load;
a first branch connecting the power source input node to the load output node via a first transistor in series with a second transistor;
an output of a first OR-circuit to operate the gate of the first transistor, wherein the output of the first OR-circuit is based on an OR combination of A and B control inputs;
a C control input to operate the gate of the second transistor;
a second branch connecting the power source input node to the load output node via a third transistor in series with a fourth transistor; and
an output of a second OR-circuit to operate the gate of the third transistor, wherein
the output of the second OR-circuit is based on an OR combination of the B and the C control inputs,
the A control input is configured to operate the gate of the fourth transistor, and
the load output node conditionally provides the voltage and the current to the load based on a majority of the A, B, and C control inputs being in an on-state.
2 . The electrical circuit of claim 1 , wherein the first and the second OR-circuits, the first and the second branches, the first, the second, the third, and the fourth transistors are all on a single circuit board.
3 . The electrical circuit of claim 2 , wherein the single circuit board is at least partially radiation-hardened.
4 . The electrical circuit of claim 1 , wherein the first, the second, the third, and the fourth transistors are each SiC MOSFETs.
5 . The electrical circuit of claim 1 , wherein the first, the second, the third, and the fourth transistors are each power FETs.
6 . The electrical circuit of claim 1 , wherein states of the A, B, and C control inputs are generated by a processor.
7 . The electrical circuit of claim 6 , wherein the first and the second OR-circuits each comprise two transistors in parallel with each other, and wherein voltage on the gate of each of the two transistors is controlled, respectively, by one of the A, B, or C control inputs generated by the processor.
8 . A majority-vote, single fault tolerant power switch comprising:
a first branch including a first transistor and a second transistor in series with the first transistor;
a second branch in parallel with the first branch and including a third transistor and a fourth transistor in series with the third transistor;
an output of a first OR-circuit applied to the gate of the first transistor;
an output of a second OR-circuit applied to the gate of the third transistor;
a first switch control node applied to a first input of the first OR-circuit and to the gate of the fourth transistor;
a second switch control node applied to a second input of the first OR-circuit and to a first input of the second OR-circuit; and
a third switch control node applied to a second input of the second OR-circuit and to the gate of the second transistor,
wherein the power switch is in an on-state if at least any two of the first, second, and third switch control nodes are in an on-state.
9 . The power switch of claim 8 , wherein the first and the second OR-circuits, the first and the second branches, the first, the second, the third, and the fourth transistors are all on a single circuit board.
10 . The power switch of claim 9 , wherein the single circuit board is at least partially radiation-hardened.
11 . The power switch of claim 8 , wherein the first, the second, the third, and the fourth transistors are each SiC MOSFETs.
12 . The power switch of claim 8 , wherein the first, the second, the third, and the fourth transistors are each P-channel power FETs.
13 . The power switch of claim 8 , wherein a processor generates signals to establish voltages levels for the first, second, and third switch control nodes.
14 . The power switch of claim 8 , wherein the first and the second OR-circuits each comprise two transistors in parallel with each other, and wherein voltage on the gate of each of the two transistors is controlled, respectively, by one of the first, second, and third switch control nodes.
15 . A single fault tolerant power switch operated by a majority-vote of three switch controllers, the single fault tolerant power switch comprising:
a first switch controller and a second switch controller in an OR-configuration configured to control a first transistor in a first circuit branch;
a third switch controller configured to control a second transistor in the first circuit branch;
the second switch controller and the third switch controller in an OR-configuration configured to control a first transistor in a second circuit branch that is in parallel to the first circuit branch; and
the first switch controller configured to control a second transistor in the second circuit branch,
wherein the single fault tolerant power switch is in an on-state if at least any two of the first, second, and third switch controllers are in an on-state.
16 . The single fault tolerant power switch of claim 15 , wherein the first and the second circuit branches, the first switch controller and the second switch controller in the OR-configuration, and the second switch controller and the third switch controller in the OR-configuration are all on a single circuit board.
17 . The single fault tolerant power switch of claim 16 , wherein the single circuit board is at least partially radiation-hardened.
18 . The single fault tolerant power switch of claim 15 , wherein the first and the second transistors in the first circuit branch and the first and the second transistors in the second circuit branch are each P-channel power FETs.
19 . The single fault tolerant power switch of claim 15 , wherein states of the first, the second, and the third switch controllers are generated by a processor.
20 . The single fault tolerant power switch of claim 15 , wherein
the first switch controller and the second switch controller in the OR-configuration comprise a first pair of transistors in parallel with each other,
voltage on the gate of each of the first pair of transistors is controlled, respectively, by one of the first, the second, and the third switch controllers,
the second switch controller and the third switch controller in the OR-configuration comprise a second pair of transistors in parallel with each other, and
voltage on the gate of each of the second pair of transistors is controlled, respectively, by one of the first, the second, and the third switch controllers.