Interface circuit and semiconductor output circuit device including the same

1 . A memory controller connected to a memory device for storing data, the memory controller comprising:

a first pad configured to receive a first voltage;

a second pad configured to receive a second voltage; and

an interface circuit configured to convert an input data signal into an output data signal between the memory controller and the memory device,

wherein the interface circuit includes a transistor having a thin gate oxide connected to the first pad and a transistor having a thick gate oxide connected to the second pad, the transistor having the thin gate oxide and the transistor having the thick gate oxide electrically connected to a third pad configured to output the output data signal, and

wherein the interface circuit is connected between the first pad and the second pad, and

wherein the interface circuit includes a first electrostatic discharge circuit electrically coupled to the first pad to protect a circuit from electrostatic electricity and a second electrostatic discharge circuit electrically coupled to the second pad to protect a circuit from electrostatic electricity.

2 . The memory controller of claim 1 , wherein a driving voltage of the memory device is lower than a driving voltage of the memory controller, and

wherein the driving voltage of the memory device includes the first voltage and the driving voltage of the memory controller includes the second voltage greater than the first voltage.

3 . The memory controller of claim 1 , wherein the first pad receives a selected one of about 1.8V, about 1.2V, and about 0.8V, as the first voltage.

4 . The memory controller of claim 1 , wherein the second pad receives a selected one of about 3.3V, about 2.5V, and about 1.8V, as the second voltage.

5 . The memory controller of claim 1 , wherein the interface circuit is configured to receive the first voltage and the second voltage which is greater than the first voltage, and

wherein the interface circuit is configured to convert a voltage level of the input data signal from a low voltage level to a high voltage level, or from the high voltage level to the low voltage level.

6 . The memory controller of claim 1 , wherein the interface circuit is electrically connected between the third pad and an internal circuit block that is integrated in the memory device.

7 . The memory controller of claim 1 , wherein the interface circuit includes:

a pull-up driver including a first PMOS transistor connected to a power terminal to which the second voltage is provided, a second PMOS transistor connected to the first PMOS transistor, and an impedance controller connected between the second PMOS transistor and a connection node which the third pad is electrically connected.

8 . The memory controller of claim 7 , wherein the first PMOS transistor and the second PMOS transistor are driven by a driving voltage and a difference between a first bias voltage and a voltage of a connection node between the first PMOS transistor and the second PMOS transistor is within a maximum operating voltage of the first and second PMOS transistors.

9 . The memory controller of claim 1 , wherein the interface circuit includes:

a pull-down driver including an impedance controller connected to a connection node which the third pad is electrically connected, a first NMOS transistor connected to the impedance controller, and a second NMOS transistor connected between the first NMOS transistor and a ground voltage terminal.

10 . The memory controller of claim 9 , wherein the first transistor and second NMOS transistor are driven between 0V and an absolute value of a maximum operating voltage, and

wherein the maximum operating voltage is 1.1 times to 1.2 times the first voltage.

11 . The memory controller of claim 1 , wherein the interface circuit includes:

a driver bias controller configured to receive the first voltage and the second voltage and generate a first bias voltage provided to a gate of a PMOS transistor and a second bias voltage provided to a gate of an NMOS transistor, each of the PMOS transistor and the NMOS transistor being the transistor having the thin gate oxide.

12 . The memory controller of claim 1 , wherein the interface circuit includes an electrostatic discharge block connected to-between the transistor having the thick gate oxide and the third pad.

13 . The memory controller of claim 1 , wherein the transistor having the thin gate oxide is a first low voltage transistor, the interface circuit further includes a second low voltage transistor and a third low voltage transistor, the second low voltage transistor is connected between the transistor having the thick gate oxide and the third pad, and the third low voltage transistor is connected between the first low voltage transistor and a ground, and

wherein the first and third low voltage transistors of the interface circuit are operated at the first voltage.

14 . The memory controller of claim 1 , wherein the interface circuit includes an electrostatic discharge block including an electrostatic detection circuit, and

wherein the electrostatic detection circuit is configured to set a first setup voltage based on a first control voltage generated by dividing the second voltage, and generate an electrostatic detection signal by detecting static electricity included in the first setup voltage.

15 . The memory controller of claim 1 , wherein the interface circuit further comprises an output driving circuit including a pull-down driver and a voltage stabilizer connected to an input/output pad, and

wherein the pull-down driver and the voltage stabilizer receive the first and second voltages as a power voltage.

16 . The memory controller of claim 15 , wherein the pull-down driver includes first, second, and third transistors connected in series between the second pad and a ground voltage terminal.

17 . The memory controller of claim 16 , further comprising:

an input/output control logic configured to receive a clock signal and an enable signal and output a first control signal to the third transistor; and

a gate control logic configured to receive a voltage of the input/output pad and output a feedback voltage to a gate terminal of the first transistor of the pull-down driver.

18 . The memory controller of claim 15 , wherein the voltage stabilizer is configured to generate a stabilization voltage based on a voltage of the input/output pad and the power voltage, and output the stabilization voltage to a control terminal of a transistor.

19 . The memory controller of claim 15 , wherein when a voltage of the input/output pad has a first value and the power voltage has a second value less than the first value, the voltage stabilizer divides the voltage of the input/output pad and generates a stabilization voltage based on a divided voltage of the pad which outputs an output signal.

20 . The memory controller of claim 19 , wherein when the power voltage has a third value greater than the second value and less than the first value, the voltage stabilizer outputs the power voltage as the stabilization voltage.

21 . The memory controller of claim 15 , wherein the voltage stabilizer comprises a first stabilizing transistor and a second stabilizing transistor between the power voltage and a first internal node outputting a divided voltage,

wherein the second stabilizing transistor is connected to a control terminal, and

wherein the voltage stabilizer outputs a voltage of a second internal node corresponding a connection node between the first and second stabilizing transistors, as the stabilization voltage.

22 . The memory controller of claim 15 , wherein the voltage stabilizer comprises:

a voltage divider connected between the input/output pad and a ground voltage terminal, the voltage divider being configured to divide a voltage of the input/output pad and to output a divided voltage to an internal node of the voltage divider;

a stabilization voltage generator connected between the power voltage and the internal node, and

wherein the stabilization voltage generator outputs a stabilization voltage based on the power voltage.

23 . The memory controller of claim 1 , wherein the interface circuit further comprises an output driving circuit comprising a pull-up-pull-down driver, a pre-driver, a level shifter, and a driver control logic, each of the level shifter and the driver control logic is connected between the pre-driver and the pull-up-pull-down driver, and the pull-up-pull down driver includes the transistor having the thick gate oxide and the transistor having the thin gate oxide.

24 . The memory controller of claim 23 , wherein the pull-up-pull-down driver comprises:

a pull-up driver connected between the second voltage and the third pad and receiving a first control signal and a second bias voltage; and

a pull-down driver connected between the third pad and a ground and receiving a second control signal and the first voltage.

25 . The memory controller of claim 23 , wherein the input data signal is a first data signal, the pre-driver is configured to receive the first data signal and generate a second data signal based on the first data signal, and

wherein the level shifter is driven based on the first voltage and the second voltage that is greater than the first voltage, and is configured to level shift the second data signal inputted through an input terminal of the level shifter, to generate a first control signal, and to apply the first control signal to the pull-up-pull-down driver.

26 . The memory controller of claim 23 , wherein the level shifter comprises:

a compensation voltage generator connected to a power terminal for receiving the second voltage and configured to generate a compensation voltage.

27 . The memory controller of claim 23 , wherein the level shifter comprises:

an output voltage compensator connected to a power terminal for receiving the second voltage and configured to adjust a voltage level of an output terminal of the level shifter according to a compensation voltage.

28 . The memory controller of claim 23 , wherein the level shifter comprises:

a current mirror receiving a data signal according to the first voltage and configured to mirror a current corresponding to the second voltage according to a level of the data signal and to generate the first control signal.

29 . The memory controller of claim 23 , wherein the level shifter comprises:

a first adjustment circuit connected to an output terminal of a current mirror, and configured to adjust a voltage level of the output terminal of the current mirror according to a first bias voltage, the first bias voltage being less than the second voltage.

30 . The memory controller of claim 23 , wherein the level shifter comprises:

a second adjustment circuit including a compensation voltage generator and an output voltage compensator which are connected in parallel with a current mirror, and configured to adjust a voltage level of an output terminal of the current mirror.

31 . The memory controller of claim 23 , wherein the level shifter comprises:

a third adjustment circuit configured to adjust voltage levels of first and second current paths of a current mirror according to the first voltage, and configured to block a current of the second current path of the current mirror according to a data signal.

32 . The memory controller of claim 23 , wherein the input data signal is a first data signal, the pre-driver is configured to receive the first data signal and generate a second data signal based on the first data signal, and the driver control logic is configured to operate based on the first voltage, to generate a second control signal based on the second data signal, and to apply the second control signal to the pull-up-pull-down driver.

33 . The memory controller of claim 23 , wherein the interface circuit further comprises a driver bias controller for controlling the pull-up-pull-down driver based on a pad voltage received through the third pad and a second bias voltage, and

wherein the driver bias controller comprises a pad-state detector detecting a voltage level of the third pad through an internal resistor and outputting a detection result to an output node of the driver bias controller.

34 . A memory controller connected to a memory device for storing data, the memory controller comprising:

a first pad configured to receive a first voltage;

a second pad configured to receive a second voltage; and

an interface circuit configured to convert an input data signal into an output data signal between the memory controller and the memory device,

wherein the interface circuit includes a first transistor connected to the first pad and a second transistor connected to the second pad, each of the first and second transistors having a thin gate oxide, the first and second transistors are electrically connected to a third pad configured to output the output data signal, and

wherein the interface circuit is connected between the first pad and the second pad, and

wherein the interface circuit includes a first electrostatic discharge circuit electrically coupled to the first pad to protect a circuit from electrostatic electricity and a second electrostatic discharge circuit electrically coupled to the second pad to protect a circuit from electrostatic electricity.