Fractional frequency-divider circuit

1 . An apparatus, comprising:

a phase generation circuit configured to:

receive an input clock signal with a first frequency; and

generate a plurality of phase signals using the input clock signal;

wherein the phase generator circuit includes:

a frequency divider circuit configured to generate a different clock signal with a third frequency, wherein a second ratio of the first frequency to the third frequency is an integer value; and

a delay-locked loop circuit configured to generate the plurality of phase signals using the different clock signal; and

a phase selection circuit configured to;

combine pairs of the plurality of phase signals to generate corresponding ones of a plurality of local clock signals;

generate a plurality of selection signals using the plurality of local clock signals; and

select, using the plurality of selection signals, different phase signals of the plurality of phase signals at corresponding times to generate an output clock signal with a second frequency, wherein a ratio of the first frequency to the second frequency is a non-integer value.

2 . The apparatus of claim 1 , wherein to combine the pairs of the plurality of phase signals, the phase selection circuit is further configured to perform an exclusive-OR operation on a first phase signal of the plurality of phase signals and a second phase signal of the plurality of phase signals to generate a particular local clock signal of the plurality of local clock signals.

3 . The apparatus of claim 1 , wherein the phase selection circuit includes a plurality of flip-flop circuits coupled together along with an inverter circuit to form a daisy chain, wherein the plurality of flip-flop circuits includes a given flip-flop circuit that includes a primary-stage circuit and a secondary-stage circuit, wherein the given flip-flop circuit is configured to transfer data from the primary-stage circuit to the secondary-stage circuit using a corresponding one of the local clock signals, and wherein to generate the plurality of selection signals, the phase selection circuit is further configured to combine a first latched signal from a particular flip-flop circuit of the plurality of flip-flop circuits and a second latched signal from a different flip-flop circuit of the plurality of flip-flop circuits, wherein the different flip-flop circuit is subsequent to the particular flip-flop circuit in the daisy chain.

4 . The apparatus of claim 1 , wherein the frequency divider circuit includes a plurality of flip-flop circuits that include a particular flip-flop circuit whose clock input is could to a complement output of a different flip-flop circuit of the plurality of flip-flop circuits.

5 . A method, comprising:

receiving, by a phase generation circuit, an input clock signal with a first frequency;

generating, by the phase generation circuit, a plurality of phase signals using the input clock signal, wherein the plurality of phase signals are delayed from the input clock signal by corresponding delay times;

combining, by a phase selection circuit, pairs of the plurality of phase signals to generate corresponding ones of a plurality of local clock signals;

generating, by the phase selection circuit, a plurality of selection signals using the plurality of local clock signals; and

selecting, by the phase selection circuit using the plurality of local clock signals, different phase signals of the plurality of phase signals at corresponding times to generate an output clock signal with a second frequency, wherein a first ratio of the first frequency to the second frequency is a non-integer value; and

wherein generating the plurality of phase signals includes:

generating, by a frequency divider circuit using the input clock signal, a different clock signal with a third frequency, wherein a second ratio of the first frequency to the third frequency is an integer value; and

delaying, by a delay-locked loop circuit, the different clock signal by different delay values to generate corresponding ones of the plurality of phase signals.

6 . The method of claim 5 , wherein combining the pairs of the plurality of phase signals includes performing an exclusive-OR operation on a first phase signal of the plurality of phase signals and a second phase signal of the plurality of phase signals to generate a particular local clock signal of the plurality of local clock signals.

7 . The method of claim 5 , wherein generating the plurality of selection signals includes combining a first latched signal from a particular flip-flop circuit of a plurality of flip-flop circuits and a second latched signal from a different flip-flop circuit of the plurality of flip-flop circuits, wherein the plurality of flip-flop circuits are coupled together along with an inverter circuit to form a daisy chain, wherein the plurality of flip-flop circuits includes a given flip-flop circuit that includes a primary-stage circuit and a secondary-stage circuit, wherein the given flip-flop circuit is configured to transfer data from the primary-stage circuit to the secondary-stage circuit using a corresponding one of the local clock signals, and wherein the different flip-flop circuit is subsequent to the particular flip-flop circuit in the daisy chain.

8 . The method of claim 5 , further comprising generating, by a frequency-divider circuit, a reduced-frequency output clock signal using the output clock signal, wherein the third frequency of the reduced-frequency output clock signal is less than the first frequency.

9 . The method of claim 5 , wherein generating, by the frequency divider circuit using the input clock signal, the different clock signal includes:

clocking a first flip-flop circuit of a plurality of flip-flop circuits using the input clock signal; and

clocking a second flip-flop circuit of the plurality of flip-flop circuits using a signal generated by the first flip-flop circuit.

10 . An apparatus, comprising:

a first device coupled to a communication bus; and

a second device coupled to the communication bus, wherein the second device includes a transceiver circuit that includes a fractional frequency-divider circuit configured to:

receive an input clock signal with a first frequency;

generate a plurality of phase signals using the input clock signal, wherein the plurality of phase signals are delayed from the input clock signal by corresponding delay times;

combine pairs of the plurality of phase signals to generate corresponding ones of a plurality of local clock signals;

generate a plurality of selection signals using the plurality of local clock signals; and

select, using the plurality of local clock signal, different phase signals of the plurality of phase signals at corresponding times to generate an output clock signal with a second frequency, wherein a first ratio of the first frequency to the second frequency is a non-integer value; and

wherein the transceiver circuit is configured to transmit data to the first device using the output clock signal; and

wherein the fractional frequency-divider circuit includes a delay-locked loop circuit, and wherein to generate the plurality of phase signals, the fractional frequency-divider circuit is further configured to:

generate, using the input clock signal, a different clock signal with a third frequency, wherein a second ratio of the first frequency to the third frequency is an integer value; and

delay, using the delay-locked loop circuit, the different clock signal by different delay values to generate corresponding ones of the plurality of phase signals.

11 . The apparatus of claim 10 , wherein to combine the pairs of the plurality of phase signals, the fractional frequency-divider circuit is configured to perform an exclusive-OR operation on a first phase signal of the plurality of phase signals and a second phase signal of the plurality of phase signals to generate a particular local clock signal of the plurality of local clock signals.

12 . The apparatus of claim 10 , wherein the fractional frequency-divider circuit includes a plurality of flip-flop circuits coupled together along with an inverter circuit to form a daisy chain, wherein the plurality of flip-flop circuits includes a given flip-flop circuit that includes a primary-stage circuit and a secondary-stage circuit, wherein the given flip-flop circuit is configured to transfer data from the primary-stage circuit to the secondary-stage circuit using a corresponding one of the local clock signals, wherein to generate the plurality of selection signals, the fractional frequency-divider circuit is further configured to combine a first latched signal from a particular flip-flop circuit of the plurality of flip-flop circuits and a second latched signal from a different flip-flop circuit of the plurality of flip-flop circuits, and wherein the different flip-flop circuit is subsequent to the particular flip-flop circuit in the daisy chain.

13 . The apparatus of claim 10 , wherein the fractional frequency-divider circuit is further configured to generate a reduced-frequency output clock signal using the output clock signal, wherein the third frequency of the reduced-frequency output clock signal is less than the first frequency.

14 . The apparatus of claim 10 , wherein the fractional frequency-divider circuit includes a plurality of flip-flop circuits and wherein to generate the different clock signal the fractional frequency-divider circuit is configured to:

generate, using a first flip-flop circuit of the plurality of flip-flop circuits, a first clock signal; and

generate, using a second flip-flop circuit of the plurality of flip-flop circuits and the first clock signal, a second clock signal.