IP Library › Granted Patent US 12706612
Granted Patent B2
US 12706612 · App. 18/742,244 · Granted Aug 11, 2026

Semiconductor integrated circuit and receiver device

Inventor: Huy Cu Ngo (Isehara, JP)
Assignee: Kioxia Corporation
H03M1/1245G11C27/024H03M1/1215
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Quick Facts
Patent No.
US 12706612
App. No.
18/742,244
Granted
Aug 11, 2026
Kind
B2
Abstract

According to one embodiment, a semiconductor integrated circuit includes: a first buffer including an input end to which a first signal is configured to be supplied; a first switching element including a first end coupled to an output end of the first buffer and a second end coupled to a first node; a first capacitor including a first end coupled to the first node and a grounded second end; a second switching element including a first end coupled to the first node and a second end coupled to a second node; a second buffer including an input end coupled to the second node; and a first converter configured to determine a first bit string from a first output from the second buffer. The first and second switching elements being configured to switch between states based on a first clock signal.

Claims (81)

1 . A semiconductor integrated circuit comprising:

a first buffer including an input end to which a first signal is configured to be supplied;

a first switching element including a first end coupled to an output end of the first buffer and a second end coupled to a first node, the first switching element being configured to switch between states based on a first clock signal;

a first capacitor including a first end coupled to the first node and a grounded second end;

a second switching element including a first end coupled to the first node and a second end coupled to a second node, the second switching element being configured to switch between states based on the first clock signal;

a second buffer including an input end coupled to the second node;

a third buffer including an input end to which a second signal is configured to be supplied, the first signal and the second signal constituting differential signals;

a third switching element including a first end coupled to an output end of the third buffer and a second end coupled to a third node, the third switching element being configured to switch between states based on the first clock signal;

a second capacitor including a first end coupled to the third node and a grounded second end;

a fourth switching element including a first end coupled to the third node and a second end coupled to a fourth node, the fourth switching element being configured to switch between states based on the first clock signal;

a fourth buffer including an input end coupled to the fourth node; and

a first converter configured to determine a first bit string from a first output from the second buffer and a second output from the fourth buffer.

2 . The semiconductor integrated circuit according to claim 1 , wherein

the first switching element is configured to be turned to an on state in a case where the first clock signal is at a first logical level, and to be turned to an off state in a case where the first clock signal is at a second logical level different from the first logical level, and

the second switching element is configured to be turned to an off state in the case where the first clock signal is at the first logical level, and to be turned to an on state in the case where the first clock signal is at the second logical level.

3 . The semiconductor integrated circuit according to claim 1 , wherein

the first switching element and the third switching element are configured to be turned to an on state in a case where the first clock signal is at a first logical level, and to be turned to an off state in a case where the first clock signal is at a second logical level different from the first logical level, and

the second switching element and the fourth switching element are configured to be turned to an off state in the case where the first clock signal is at the first logical level, and to be turned to an on state in the case where the first clock signal is at the second logical level.

4 . The semiconductor integrated circuit according to claim 1 , further comprising:

a fifth switching element including a first end coupled to the second node and a second end coupled to the fourth node, the fifth switching element being configured to switch between states based on the first clock signal; and

a sixth switching element including a first end coupled to an output end of the second buffer and a second end coupled to an output end of the fourth buffer, the sixth switching element being configured to switch between states based on the first clock signal.

5 . The semiconductor integrated circuit according to claim 4 , wherein

the first switching element, the third switching element, the fifth switching element, and the sixth switching element are configured to be turned to an on state in a case where the first clock signal is at a first logical level, and to be turned to an off state in a case where the first clock signal is at a second logical level different from the first logical level, and

the second switching element and the fourth switching element are configured to be turned to an off state in the case where the first clock signal is at the first logical level, and to be turned to an on state in the case where the first clock signal is at the second logical level.

6 . The semiconductor integrated circuit according to claim 1 , further comprising:

a seventh switching element including a first end coupled to the second node and a second end coupled to an output end of the second buffer, the seventh switching element being configured to switch between states based on the first clock signal; and

an eighth switching element including a first end coupled to the fourth node and a second end coupled to an output end of the fourth buffer, the eighth switching element being configured to switch between states based on the first clock signal.

7 . The semiconductor integrated circuit according to claim 6 , wherein

the first switching element, the third switching element, the seventh switching element, and the eighth switching element are configured to be turned to an on state in a case where the first clock signal is at a first logical level, and to be turned to an off state in a case where the first clock signal is at a second logical level different from the first logical level, and

the second switching element and the fourth switching element are configured to be turned to an off state in the case where the first clock signal is at the first logical level, and to be turned to an on state in the case where the first clock signal is at the second logical level.

8 . The semiconductor integrated circuit according to claim 1 , further comprising:

a ninth switching element including a first end coupled to the second node and a grounded second end, the ninth switching element being configured to switch between states based on the first clock signal;

a tenth switching element including a first end coupled to an output end of the second buffer and a grounded second end, the tenth switching element being configured to switch between states based on the first clock signal;

an eleventh switching element including a first end coupled to the fourth node and a grounded second node, the eleventh switching element being configured to switch between states based on the first clock signal; and

a twelfth switching element including a first end coupled to an output end of the fourth buffer and a grounded second end, the twelfth switching element being configured to switch between states based on the first clock signal.

9 . The semiconductor integrated circuit according to claim 8 , wherein

the first switching element, the third switching element, the ninth switching element, the tenth switching element, the eleventh switching element, and the twelfth switching element are configured to be turned to an on state in a case where the first clock signal is at a first logical level, and to be turned to an off state in a case where the first clock signal is at a second logical level different from the first logical level, and

the second switching element and the fourth switching element are configured to be turned to an off state in the case where the first clock signal is at the first logical level, and to be turned to an on state in the case where the first clock signal is at the second logical level.

10 . A receiver device comprising:

a semiconductor integrated circuit; and

a processing circuit configured to process a signal output from the semiconductor integrated circuit,

wherein the semiconductor integrated circuit includes:

a first buffer including an input end to which a first signal is configured to be supplied;

a first switching element including a first end coupled to an output end of the first buffer and a second end coupled to a first node, the first switching element being configured to switch between states based on a first clock signal;

a first capacitor including a first end coupled to the first node and a grounded second end;

a second switching element including a first end coupled to the first node and a second end coupled to a second node, the second switching element being configured to switch between states based on the first clock signal;

a second buffer including an input end coupled to the second node;

a third buffer including an input end to which a second signal is configured to be supplied, the first signal and the second signal constituting differential signals;

a third switching element including a first end coupled to an output end of the third buffer and a second end coupled to a third node, the third switching element being configured to switch between states based on the first clock signal;

a second capacitor including a first end coupled to the third node and a grounded second end;

a fourth switching element including a first end coupled to the third node and a second end coupled to a fourth node, the fourth switching element being configured to switch between states based on the first clock signal;

a fourth buffer including an input end coupled to the fourth node; and

a first converter configured to determine a first bit string from a first output from the second buffer and a second output from the fourth buffer.

11 . The receiver device according to claim 10 , wherein

the first switching element is configured to be turned to an on state in a case where the first clock signal is at a first logical level, and to be turned to an off state in a case where the first clock signal is at a second logical level different from the first logical level, and

the second switching element is configured to be turned to an off state in the case where the first clock signal is at the first logical level, and to be turned to an on state in the case where the first clock signal is at the second logical level.

12 . The receiver device according to claim 10 , wherein

the first switching element and the third switching element are configured to be turned to an on state in a case where the first clock signal is at a first logical level, and to be turned to an off state in a case where the first clock signal is at a second logical level different from the first logical level, and

the second switching element and the fourth switching element are configured to be turned to an off state in the case where the first clock signal is at the first logical level, and to be turned to an on state in the case where the first clock signal is at the second logical level.

13 . The receiver device according to claim 10 , wherein

the semiconductor integrated circuit further comprises:

a fifth switching element including a first end coupled to the second node and a second end coupled to the fourth node, the fifth switching element being configured to switch between states based on the first clock signal; and

a sixth switching element including a first end coupled to an output end of the second buffer and a second end coupled to an output end of the fourth buffer, the sixth switching element being configured to switch between states based on the first clock signal.

14 . The receiver device according to claim 13 , wherein

the first switching element, the third switching element, the fifth switching element, and the sixth switching element are configured to be turned to an on state in a case where the first clock signal is at a first logical level, and to be turned to an off state in a case where the first clock signal is at a second logical level different from the first logical level, and

the second switching element and the fourth switching element are configured to be turned to an off state in the case where the first clock signal is at the first logical level, and to be turned to an on state in the case where the first clock signal is at the second logical level.

15 . The receiver device according to claim 10 , wherein the semiconductor integrated circuit further comprises:

a seventh switching element including a first end coupled to the second node and a second end coupled to an output end of the second buffer, the seventh switching element being configured to switch between states based on the first clock signal; and

an eighth switching element including a first end coupled to the fourth node and a second end coupled to an output end of the fourth buffer, the eighth switching element being configured to switch between states based on the first clock signal.

16 . The receiver device according to claim 15 , wherein

the first switching element, the third switching element, the seventh switching element, and the eighth switching element are configured to be turned to an on state in a case where the first clock signal is at a first logical level, and to be turned to an off state in a case where the first clock signal is at a second logical level different from the first logical level, and

the second switching element and the fourth switching element are configured to be turned to an off state in the case where the first clock signal is at the first logical level, and to be turned to an on state in the case where the first clock signal is at the second logical level.

17 . The receiver device according to claim 10 , wherein

the semiconductor integrated circuit further comprises:

a ninth switching element including a first end coupled to the second node and a grounded second end, the ninth switching element being configured to switch between states based on the first clock signal;

a tenth switching element including a first end coupled to an output end of the second buffer and a grounded second end, the tenth switching element being configured to switch between states based on the first clock signal;

an eleventh switching element including a first end coupled to the fourth node and a grounded second node, the eleventh switching element being configured to switch between states based on the first clock signal; and

a twelfth switching element including a first end coupled to an output end of the fourth buffer and a grounded second end, the twelfth switching element being configured to switch between states based on the first clock signal.

18 . The receiver device according to claim 17 , wherein

the first switching element, the third switching element, the ninth switching element, the tenth switching element, the eleventh switching element, and the twelfth switching element are configured to be turned to an on state in a case where the first clock signal is at a first logical level, and to be turned to an off state in a case where the first clock signal is at a second logical level different from the first logical level, and

the second switching element and the fourth switching element are configured to be turned to an off state in the case where the first clock signal is at the first logical level, and to be turned to an on state in the case where the first clock signal is at the second logical level.