Decoder circuit and decoding method capable of reducing number of read/write of memory to reduce power consumption

1 . A decoder circuit, comprising:

a channel value memory, for receiving and storing an input data as a channel value, the channel value being stored in the channel value memory in a form of a sign bit with multiple magnitude bits;

a sign memory, for storing a sign value;

a gradient descent bit memory, for storing a difference information corresponding to the channel value;

a variable node unit, coupled to the channel value memory, the sign memory, and the gradient descent bit memory, for generating a first output value and a second output value according to the channel value;

a first barrel shifter, coupled to the variable node unit, for converting the first output value from a variable node domain to a check node domain to generate a converted first output value;

a check node unit, coupled to the first barrel shifter, for generating a check-to-variable message based on the converted first output value or the sign value stored in the sign memory;

a second barrel shifter, coupled to the check node unit, for converting the check-to-variable message from the check node domain to the variable node domain to generate a converted check-to-variable message to the variable node unit; and

a decision bit output unit, coupled to the gradient descent bit memory and the channel value memory, for generating and determining an output data according to the channel value in the channel value memory and the difference information corresponding to the channel value stored in the gradient descent bit memory.

2 . The decoder circuit of claim 1 , wherein when performing an iterative decoding operation for a first time: the variable node unit reads the sign bit and the multiple value bits, corresponding to the channel value, from the channel value memory, and uses the channel value as the first output value; the first barrel shifter converts the first output value from the variable node domain to the check node domain to generate the converted first output value; the check node unit performs a minimization calculation according to the converted first output value to generate and output the check-to-variable message without reading the sign memory; and, the second barrel shifter converts the check-to-variable message from the check node domain to the variable node domain to generate the converted check-to-variable message.

3 . The decoder circuit of claim 2 , wherein when the iterative decoding operation is performed for a second time, the variable node unit generates and updates the first output value according to a following equation:

qval_out

i

=

abs

⁡

(

ch_v

)

+

∑

R

-

R

i

;

wherein qval_out i is the first output value generated and updated by the iterative decoding operation performed for the second time; abs(ch_v) is an absolute values of the channel value ch_v, and the variable node during the iterative decoding operation performed for the second time merely reads the multiple magnitude bits from the channel value memory to calculate the absolute value, without reading the sign bit of the channel value; ΣR is a sum of multiple converted check-to-variable messages of multiple adjacent bits previously generated by the variable node unit; R i is a converted check-to-variable message generated by the second barrel shifter during a previous iterative decoding operation; and, the variable node unit writes and stores an absolute value of the first output value into the sign memory when performing the iterative decoding operation for the second time.

4 . The decoder circuit of claim 3 , wherein when performing the iterative decoding operation for more than a third time, the variable node unit reads a previous sign value from the sign memory stored by a previous iterative decoding operation, compares the previous sign value with a current sign value of the first output value; and, only when the previous sign value is different from the current sign value of the first output value, the variable node unit writes the current sign value of the first output value to the sign memory to replace the previous sign value.

5 . The decoder circuit of claim 1 , wherein when performing an iterative decoding operation for a first time, the variable node unit reads the sign bit and the magnitude bits, corresponding to the channel value, from the channel value memory, and uses the channel value as the second output value, wherein the second output value is not written into the gradient descent bit memory by the variable node unit.

6 . The decoder circuit of claim 5 , wherein when the second iterative decoding operation is performed for a second time, the variable node unit generates and updates the second output value according to a following equation:

app_out

=

abs

⁡

(

ch_v

)

+

∑

R

;

wherein app_out is the second output value generated and updated by the iterative decoding operation performed for the second time; abs(ch_v) is an absolute value of the channel value; ΣR is a sum of multiple converted check-to-variable messages of multiple adjacent bits previously generated by the variable node unit; the variable node unit writes an absolute value of the updated second output value into the gradient descent bit memory as the difference information corresponding to the channel value during the iterative decoding operation performed for the second time.

7 . The decoder circuit of claim 6 , wherein when performing the iterative decoding operation for more than a third time, the variable node unit generates and updates the second output value based on an equation of app_out=abs(ch_v)+ΣR; the variable node unit reads a previous sign value, which is stored in the gradient descent bit memory by the iterative decoding operation performed previously, from the gradient descent bit memory, and compares the previous sign value in the gradient descent bit memory with a current sign value of the second output value; and, only when the previous sign value in the gradient descent bit memory is different from the current sign value of the second output value, the variable node unit writes the current sign value of the second output value into the gradient descent bit memory and updates the difference information corresponding to the channel value.

8 . The decoder circuit of claim 1 , wherein the decision bit output unit performs an exclusive-OR operation upon the channel value of the channel value memory and the difference information to perform a hard decision to generate and determine the output data.

9 . The decoder circuit of claim 1 , being used and included in a flash memory controller.

10 . A decoding method of a decoder circuit, comprising:

providing a channel value memory to receive and store an input data as a channel value, the channel value being stored in the channel value memory in a form of a sign bit with multiple magnitude bits;

providing a sign memory to store a sign value;

providing a gradient descent bit memory to store a difference information corresponding to the channel value;

providing a variable node unit to generate a first output value and a second output value according to the channel value;

providing a first barrel shifter to convert the first output value from a variable node domain to a check node domain to generate a converted first output value;

providing a check node unit to generate a check-to-variable message based on the converted first output value or the sign value stored in the sign memory;

providing a second barrel shifter to convert the check-to-variable message from the check node domain to the variable node domain to generate a converted check-to-variable message to the variable node unit; and

generating and determining an output data according to the channel value in the channel value memory and the difference information corresponding to the channel value stored in the gradient descent bit memory.

11 . The decoding method of claim 10 , further comprising:

when performing an iterative decoding operation for a first time:

using the variable node unit to read the sign bit and the multiple value bits, corresponding to the channel value, from the channel value memory, and using the channel value as the first output value;

using the first barrel shifter to convert the first output value from the variable node domain to the check node domain to generate the converted first output value;

using the check node unit to perform a minimization calculation according to the converted first output value to generate and output the check-to-variable message without reading the sign memory; and

using the second barrel shifter to convert the check-to-variable message from the check node domain to the variable node domain to generate the converted check-to-variable message.

12 . The decoding method of claim 11 , further comprising:

when the iterative decoding operation is performed for a second time, using the variable node unit to generate and update the first output value according to a following equation:

qval_out

i

=

abs

⁡

(

ch_v

)

+

∑

R

-

R

i

;

wherein qval_out i is the first output value generated and updated by the iterative decoding operation performed for the second time; abs(ch_v) is an absolute values of the channel value ch_v, and the variable node during the iterative decoding operation performed for the second time merely reads the multiple magnitude bits from the channel value memory to calculate the absolute value, without reading the sign bit of the channel value; ΣR is a sum of multiple converted check-to-variable messages of multiple adjacent bits previously generated by the variable node unit; R i is a converted check-to-variable message generated by the second barrel shifter during a previous iterative decoding operation; and, the variable node unit writes and stores an absolute value of the first output value into the sign memory when performing the iterative decoding operation for the second time.

13 . The decoding method of claim 12 , further comprising:

when performing the iterative decoding operation for more than a third time:

using the variable node unit to read a previous sign value from the sign memory stored by a previous iterative decoding operation, and comparing the previous sign value with a current sign value of the first output value; and

only when the previous sign value is different from the current sign value of the first output value, using the variable node unit to write the current sign value of the first output value to the sign memory to replace the previous sign value.

14 . The decoding method of claim 10 , further comprising:

wherein when performing an iterative decoding operation for a first time, using the variable node unit to read the sign bit and the magnitude bits, corresponding to the channel value, from the channel value memory, and to use the channel value as the second output value, wherein the second output value is not written into the gradient descent bit memory by the variable node unit.

15 . The decoding method of claim 14 , further comprising:

when the second iterative decoding operation is performed for a second time, using the variable node unit to generate and update the second output value according to a following equation:

app_out

=

abs

⁡

(

ch_v

)

+

∑

R

;

wherein app_out is the second output value generated and updated by the iterative decoding operation performed for the second time; abs(ch_v) is an absolute value of the channel value; ΣR is a sum of multiple converted check-to-variable messages of multiple adjacent bits previously generated by the variable node unit; the variable node unit writes an absolute value of the updated second output value into the gradient descent bit memory as the difference information corresponding to the channel value during the iterative decoding operation performed for the second time.

16 . The decoding method of claim 15 , further comprising:

when performing the iterative decoding operation for more than a third time:

using the variable node unit to generate and update the second output value based on an equation of app_out=abs(ch_v)+ΣR;

using the variable node unit to read a previous sign value, which is stored in the gradient descent bit memory by the iterative decoding operation performed previously, from the gradient descent bit memory, and comparing the previous sign value in the gradient descent bit memory with a current sign value of the second output value; and

only when the previous sign value in the gradient descent bit memory is different from the current sign value of the second output value, using the variable node unit to write the current sign value of the second output value into the gradient descent bit memory and update the difference information corresponding to the channel value.

17 . The decoding method of claim 10 , further comprising:

using the decision bit output unit to perform an exclusive-OR operation upon the channel value of the channel value memory and the difference information to perform a hard decision to generate and determine the output data.