Wireless transmitter with bias control

1 . An apparatus for wireless communication, comprising:

an in-phase direct-current (DC) level shifter;

a quadrature DC level shifter;

an in-phase voltage-to-current (V2I) converter having an input coupled to an output of the in-phase DC level shifter;

a quadrature V2I converter having an input coupled to an output of the quadrature V2I converter;

a bias control circuit having inputs coupled to the in-phase V2I converter and the quadrature V2I converter, an output of the bias control circuit being coupled to at least one of the in-phase DC level shifter or the quadrature DC level shifter;

an in-phase mixer having an input coupled to an output of the in-phase V2I converter; and

a quadrature mixer having an input coupled to an output of the quadrature V2I converter.

2 . The apparatus of claim 1 , wherein:

the in-phase DC level shifter comprises a first source follower circuit configured to DC level shift an in-phase signal; and

the quadrature DC level shifter comprises a second source follower circuit configured to DC level shift a quadrature signal.

3 . The apparatus of claim 2 , wherein:

the in-phase V2I converter comprises a first tail current source;

the quadrature V2I converter comprises a second tail current source; and

the bias control circuit is configured to:

sense a first drain-to-source voltage (VDS) associated with the first tail current source and a second VDS associated with the second tail current source; and

bias at least one of the first source follower circuit or the second source follower circuit based on the first VDS and the second VDS.

4 . The apparatus of claim 3 , wherein the bias control circuit comprises an amplifier having a first input configured to receive an average of the first VDS and the second VDS, a second input configured to receive a reference voltage, and an output coupled to a gate of a bias transistor of at least one of the first source follower circuit or the second source follower circuit.

5 . The apparatus of claim 2 , further comprising a phase interpolator comprising:

a first output coupled to an input of the first source follower circuit and configured to generate the in-phase signal; and

a second output coupled to an input of the second source follower circuit and configured to generate the quadrature signal.

6 . The apparatus of claim 1 , further comprising:

a current-sensing circuit having inputs coupled to a positive differential output and a negative differential output of at least one of the in-phase mixer or the quadrature mixer; and

a digital-to-analog converter (DAC) having an input coupled to the current-sensing circuit and an output coupled to the at least one of the in-phase V2I converter or the quadrature V2I converter.

7 . The apparatus of claim 6 , wherein the current-sensing circuit comprises:

a first resistive element selectively coupled to the positive differential output or the negative differential output and a second resistive element selectively coupled to the positive differential output or the negative differential output; and

an analog-to-digital converter (ADC) having a first input selectively coupled to the first resistive element and a second input selectively coupled to the second resistive element.

8 . The apparatus of claim 7 , wherein:

the ADC is configured to:

sense a first voltage at the first resistive element while the first resistive element is coupled to the positive differential output; and

sense a second voltage at the second resistive element while the second resistive element is coupled to the negative differential output; and

the DAC is configured to bias the at least one of the in-phase mixer or the quadrature mixer based on the first voltage and the second voltage using at least one of the in-phase V2I converter or the quadrature V2I converter.

9 . The apparatus of claim 8 , wherein:

the ADC is configured to:

sense a third voltage at the first resistive element while the first resistive element is coupled to the negative differential output; and

sense a fourth voltage at the second resistive element while the second resistive element is coupled to the positive differential output; and

the DAC is configured to bias the at least one of the in-phase mixer or the quadrature mixer based on the third voltage and the fourth voltage using at least one of the in-phase V2I converter or the quadrature V2I converter.

10 . The apparatus of claim 1 , wherein the in-phase mixer and the quadrature mixer comprise harmonic rejection mixers.

11 . The apparatus of claim 1 , further comprising:

a first signal path coupled to a differential output pair of at least one of the in-phase mixer or the quadrature mixer; and

a second signal path coupled to the differential output pair of at least one of the in-phase mixer or the quadrature mixer, wherein the first signal path and the second signal path are further coupled to a transmitter port of the apparatus.

12 . The apparatus of claim 11 , wherein the first signal path comprises:

a first balanced-unbalanced (balun) component having an unbalanced terminal coupled to the transmitter port;

a first switch coupled between a first differential output of the differential output pair and a first balanced terminal of the first balun component; and

a second switch coupled between a second differential output of the differential output pair and a second balanced terminal of the first balun component.

13 . The apparatus of claim 12 , wherein the second signal path comprises:

a second balun component having an unbalanced terminal coupled to the transmitter port;

a third switch coupled between the first differential output of the differential output pair and a first balanced terminal of the second balun component; and

a fourth switch coupled between the second differential output of the differential output pair and a second balanced terminal of the second balun component.

14 . The apparatus of claim 12 , wherein the first signal path further comprises:

a third switch coupled between the first differential output and the second balanced terminal; and

a fourth switch coupled between the second differential output and the first balanced terminal.

15 . The apparatus of claim 1 , further comprising a transceiver including the in-phase mixer and the quadrature mixer.

16 . The apparatus of claim 15 , wherein the transceiver is part of a base station.

17 . A method for wireless communication, comprising:

generating, via an in-phase direct-current (DC) level shifter, an in-phase level-shifted signal;

generating, via a quadrature DC level shifter, a quadrature level-shifted signal;

converting, via an in-phase voltage-to-current (V2I) converter, the in-phase level-shifted signal to an in-phase current;

converting, via a quadrature V2I converter, the quadrature level-shifted signal to a quadrature current;

sensing, via a bias control circuit, signals at nodes of the in-phase V2I converter and the quadrature V2I converter;

providing a bias signal to at least one of the in-phase DC level shifter or the quadrature DC level shifter based on the sensing;

generating, via an in-phase mixer, an upconverted in-phase signal based on the in-phase current; and

generating, via a quadrature mixer, an upconverted quadrature signal based on the quadrature current.

18 . The method of claim 17 , wherein:

the in-phase DC level shifter comprises a first source follower;

generating the in-phase level-shifted signal comprises level shifting an in-phase signal using the first source follower to generate the in-phase level-shifted signal;

the quadrature DC level shifter comprises a second source follower; and

generating the quadrature level-shifted signal comprises level shifting a quadrature signal using the second source follower to generate the quadrature level-shifted signal.

19 . The method of claim 18 , wherein:

the in-phase V2I converter comprises a first tail current source;

the quadrature V2I converter comprises a second tail current source; and

the sensed signals comprise a first drain-to-source voltage (VDS) associated with the first tail current source and a second VDS associated with the second tail current source; and

the bias signal is provided to a gate of a bias transistor of at least one of the first source follower or the second source follower.

20 . The method of claim 17 , further comprising sensing, via a current-sensing circuit, a positive differential output current and a negative differential output current of at least one of the in-phase mixer or the quadrature mixer, wherein at least one of the in-phase current or the quadrature current is generated based on the sensed positive differential output current and the sensed negative differential output current.

21 . The method of claim 17 , wherein at least one of the in-phase mixer or the quadrature mixer comprises a positive differential output and a negative differential output, the method further comprising:

sensing a first voltage at a first resistive element while the first resistive element is coupled to the positive differential output;

sensing a second voltage at a second resistive element while the second resistive element is coupled to the negative differential output; and

biasing the at least one of the in-phase mixer or the quadrature mixer based on the first voltage and the second voltage.

22 . The method of claim 21 , further comprising:

sensing a third voltage at the first resistive element while the first resistive element is coupled to the negative differential output;

sensing a fourth voltage at the second resistive element while the second resistive element is coupled to the positive differential output; and

biasing the at least one of the in-phase mixer or the quadrature mixer based on the third voltage and the fourth voltage.

23 . The method of claim 17 , wherein the in-phase mixer and the quadrature mixer comprise harmonic rejection mixers.

24 . The method of claim 17 , wherein one of the in-phase mixer or the quadrature mixer comprises a positive differential output and a negative differential output, the method further comprising:

routing, via a first switch of a first current path, at least a portion of a current from the positive differential output to a first balanced terminal of a first balanced-unbalanced (balun) component; and

routing, via a second switch of a second current path, the at least the portion of the current from a second balanced terminal of the balun component towards the negative differential output, wherein an unbalanced terminal of the balun component is coupled to a transmitter port.

25 . The method of claim 24 , further comprising routing, via a third switch, at least another portion of the current from the positive differential output to the second current path.

26 . An apparatus for wireless communication, comprising:

an in-phase direct-current (DC) level shifter;

a quadrature DC level shifter;

an in-phase voltage-to-current (V2I) converter having an input coupled to an output of the in-phase DC level shifter;

a quadrature V2I converter having an input coupled to an output of the quadrature V2I converter;

an in-phase mixer having an input coupled to an output of the in-phase V2I converter;

a quadrature mixer having an input coupled to an output of the quadrature V2I converter;

a current-sensing circuit having inputs coupled to a positive differential output and a negative differential output of at least one of the in-phase mixer or the quadrature mixer; and

a digital-to-analog converter (DAC) having an input coupled to the current-sensing circuit and an output coupled to the at least one of the in-phase V2I converter or the quadrature V2I converter.

27 . The apparatus of claim 26 , wherein the current-sensing circuit comprises:

a first resistive element selectively coupled to the positive differential output or the negative differential output and a second resistive element selectively coupled to the positive differential output or the negative differential output; and

an analog-to-digital converter (ADC) having a first input selectively coupled to the first resistive element and a second input selectively coupled to the second resistive element.

28 . The apparatus of claim 27 , wherein:

the ADC is configured to:

sense a first voltage at the first resistive element while the first resistive element is coupled to the positive differential output; and

sense a second voltage at the second resistive element while the second resistive element is coupled to the negative differential output; and

the DAC is configured to bias the at least one of the in-phase mixer or the quadrature mixer based on the first voltage and the second voltage using at least one of the in-phase V2I converter or the quadrature V2I converter.

29 . The apparatus of claim 28 , wherein:

the ADC is configured to:

sense a third voltage at the first resistive element while the first resistive element is coupled to the negative differential output; and

sense a fourth voltage at the second resistive element while the second resistive element is coupled to the positive differential output; and

the DAC is configured to bias the at least one of the in-phase mixer or the quadrature mixer based on the third voltage and the fourth voltage using at least one of the in-phase V2I converter or the quadrature V2I converter.

30 . A method for wireless communication, comprising:

generating, via an in-phase direct-current (DC) level shifter, an in-phase level-shifted signal;

generating, via a quadrature DC level shifter, a quadrature level-shifted signal;

converting, via an in-phase voltage-to-current (V2I) converter, the in-phase level-shifted signal to an in-phase current;

converting, via a quadrature V2I converter, the quadrature level-shifted signal to a quadrature current;

sensing, via a current-sensing circuit, a positive differential output current and a negative differential output current of at least one of an in-phase mixer or a quadrature mixer, wherein at least one of the in-phase current or the quadrature current is generated based on the sensed positive differential output current and the sensed negative differential output current;

generating, via the in-phase mixer, an upconverted in-phase signal based on the in-phase current; and

generating, via the quadrature mixer, an upconverted quadrature signal based on the quadrature current.