Method and system for determining a round-trip latency of a quantum communication channel

1 . A method for determining a round-trip latency of a communication channel in a quantum communication system between a first device located at a first location and a second device located at a second location that is remote from the first location, wherein the communication system comprises a clock unit configured to generate clock cycles, comprising:

setting an estimated round-trip latency value by the first device, wherein the estimated round-trip latency value is represented as a binary number and represents a latency measured in clock cycles of the clock unit;

generating and sending, during a first period, a first test signal by the first device to the second device, wherein the first test signal comprises alternating first values and second values, wherein first and second values are sent at each clock cycle of the clock unit;

saving by the first device each first and second value of the first test signal for at least a duration that corresponds to the estimated round-trip latency value;

receiving the first test signal at the second device;

sending, by the second device to the first device, upon receiving the first test signal, a validating signal that is generated by the second device and is based on the first test signal, wherein the validating signal comprises at least second values when second values from the first test signal are received;

receiving the validating signal at the first device;

comparing the validating signal with the first test signal sent during the first period; and

determining if the estimated round-trip latency value is correct based on the comparing of the validating signal and the first test signal.

2 . The method according to claim 1 , wherein comparing the validating signal with the first test signal comprises:

determining, at a time of receiving a second value from the validating signal, if the first test signal that was sent at a time that is one estimated round-trip latency value earlier than the receiving of the second value of the validating signal comprises a first or second value; and

comparing the determined first or second value of the first test signal with the second value of the validating signal.

3 . The method according to claim 1 , wherein:

saving by the first device each first and second value of the first test signal for at least a duration that corresponds to the estimated round-trip latency value comprises storing each first and second value from the first test signal in a shift register, wherein the shift register has a length that corresponds to the estimated round-rip latency value, and

when the received validating signal comprises the second value, the method further comprises:

determining, upon registering that the received validating signal comprises the second value, if an output of the shift register is a first or second value; and

comparing the determined first or second value of the output of the shift register with the second value of the validating signal.

4 . The method according to claim 1 , wherein determining if the estimated round-trip latency value is correct further comprises:

determining, based upon at least the second values of the validating signal corresponding to the sending of the second values of the first test signal, that a least significant bit of the estimated round-trip latency value is correct; and

flipping the least significant bit of the estimated round-trip latency value if the least significant bit of the estimated round-trip latency value is incorrect.

5 . The method according to claim 1 , wherein the steps of comparing the validating signal with the first test signal is repeated for a predetermined number of times, wherein each time that during a determination step the second value of the validating signal corresponds to the second value of the first test signal represents a correct measurement, and wherein determining if the estimated round-trip latency value is correct further comprises:

determining a ratio corresponding to a number of correct measurements divided by the predetermined number of times; and

determine that the least significant bit of the estimated round-trip latency value is correct if the ratio is above a predetermined threshold.

6 . The method according to claim 1 , wherein determining if the estimated round-trip latency value is correct determines if an actual round-trip latency value is a multiple of 2 clock cycles.

7 . The method according to claim 1 , further comprising:

generating and sending, during a second period, a second test signal by the first device to the second device, wherein the second test signal comprises first values and second values, wherein each second value is preceded by three first values, or

wherein determining if the estimated round-trip latency value is correct further comprises:

determining, based upon at least the second values of the validating signal corresponding to the sending of the second values of the second test signal, that a second-to-least significant bit of the estimated round-trip latency value is correct; or

wherein determining if the estimated round trip latency value is correct determines if the estimated round trip latency value is off by a multiple of a clock cycles compared to an actual round trip latency value; or

flipping the second-to-least significant bit if the second-to-least significant bit of the estimated round-trip latency value is incorrect.

8 . The method according to claim 1 , further comprising:

generating and sending, during a third period, a third test signal from the first device to the second device, wherein the third test signal comprises first values and second values, wherein each second value is preceded by seven first values; or

wherein determining if the estimated round trip latency value is correct further comprises:

determining, based upon at least the second values of the validating signal corresponding to the sending of the second values of the third test signal, that a third-to-least significant bit of the estimated round trip latency value is correct; or

wherein determining if the estimated round trip latency value is correct determines if the estimated round trip latency value is off by a multiple of 4 clock cycles compared to an actual round trip value latency value; or

flipping the third-to-least significant bit if the third-to-least significant bit of the estimated round-trip latency value is incorrect.

9 . The method according to claim 1 , further comprising:

generating and sending for n=1 till N, during a n-th period, a n-th test signal by the first device to the second device, wherein the n-th test signal comprises first and second values, wherein each second value is preceded by two to a power n minus one times a first value;

repeating the generating and sending of the test signal wherein with each repetition the value of n is increased by one; or

wherein determining if the estimated round trip latency value is correct determines if the estimated round trip latency value is off by a multiple of two to a power n−1 clock cycles compared to an actual round trip latency value, the method further comprising:

stopping the repeating of the generating of the test signal based on a distance between the first device and second device and a speed of light.

10 . The method according to claim 1 , wherein the test signals and/or validating signals are optical signals, and wherein the first and second values are early late or vacuum time bin qubits; or

wherein the clock signal is a Manchester encoded clock signal, and wherein the validating signal is encoded onto the clock signal; or

wherein the estimated round trip latency value is at least partly set based on a distance between the first and second device divided by the speed of light.

11 . A quantum communication system for determining a round-trip latency between a first and a second location of a communication channel, comprising:

a first electronic device that is positioned at the first location comprising a controller and a signal circuit;

a second electronic device that is positioned at the second location that is remote from the first location comprising a controller and a signal circuit,

a clock unit that is configured to generate clock cycles which are sent to the first and second electronic device,

wherein the controller of the first electronic device is configured to:

set an estimated round-trip latency value by the first electronic device, wherein the estimated round-trip latency value is represented as a binary number and represents a latency measured in clock cycles of the clock unit;

generate and sending, during a first period, a first test signal by the first electronic device to the second electronic device, wherein the first test signal comprises alternating first values and second values, wherein first and second values are sent at each clock cycle of the clock unit;

save by the first electronic device each first and second value of the first test signal for at least a duration that corresponds to the estimated round-trip latency value;

receive a validating signal at the first electronic device;

compare the validating signal with the first test signal sent during the first period; and

determine if the estimated round-trip latency value is correct based on the comparing of the validating signal and the first test signal,

wherein the controller of the second electronic device is configured to:

receive the first test signal at the second electronic device; and

send, to the first electronic device, upon receiving the first test signal, a validating signal that is generated by the second electronic device and is based on the first test signal, wherein the validating signal comprises at least second values when second values from the first test signal are received.

12 . The system according to claim 11 , wherein the controller of the first electronic device being configured to compare the validating signal with the first test signal comprises the controller of the first electronic device being configured to:

determine, at a time of receiving a second value from the validating signal, if the first test signal that is sent at a time that is one estimated round-trip latency value earlier than the receiving of the second value of the validating signal comprises a first or second value; and

compare the determined first or second value of the first test signal with the second value of the validating signal.

13 . The system according to claim 11 , wherein:

the controller of the first electronic device being configured to save each first and second value of the first test signal for at least a duration that corresponds to the estimated round-trip latency value comprises the controller of the first electronic device being configured to store each first and second value from the first test signal in a shift register, wherein the shift register has a length that corresponds to the estimated round-trip latency value, and

when the received validating signal comprises the second value, the controller of the first electronic device being further configured to:

determine, upon registering that the received validating signal comprises the second value, if an output of the shift register is a first or second value; and

compare the determined first or second value of the output of the shift register with the second value of the validating signal.

14 . The system according to claim 11 , wherein the controller of the first electronic device being configured to determine if the estimated round-trip latency value is correct further comprises the controller of the first electronic device being configured to:

determine, based upon at least the second values of the validating signal corresponding to the sending of the second signal of the first test signal, that a least significant bit of the estimated round-trip latency value is correct; and

flip the least significant bit of the estimated round-trip latency value if the least significant bit of the estimated round-trip latency value is incorrect.

15 . The system according to claim 11 , wherein the controller of the first electronic device being configured to compare the validating signal with the first test signal is repeated for a predetermined number of times, wherein each time during a determination the second value of the validating signal corresponds to the second value of the first test signal represents a correct measurement,

and wherein the controller of the first electronic device being configured to determine if the estimated round-trip latency value is correct further comprises the controller of the first electronic device being configured to:

determine a ratio corresponding to a number of correct measurements divided by the predetermined number of times; and

determine that the least significant bit of the estimated round-trip latency value is correct if the ratio is above a predetermined threshold; or

wherein the controller of the first electronic device being configured to determine if the estimated round-trip latency value is correct determines if an actual round-trip latency value is a multiple of 2 clock cycles.

16 . The system according to claim 11 , wherein the controller of the first electronic device is further configured to:

generate and send, during a second period, a second test signal by the first electronic device to the second electronic device, wherein the second test signal comprises first values and second values, wherein each second value is preceded by three first values; or

wherein the controller of the first electronic device is configured to determine if the estimated round trip latency value is correct further comprises:

determine, based upon at least the second values of the validating signal corresponding to the sending of the second values of the second test signal, that a second-to-least significant bit of the estimated round trip latency value is correct; or

wherein the controller of the first electronic device being configured to determine if the estimated round-trip latency value is correct determines if the estimated round-trip latency value is off by a multiple of 2 clock cycles compared to an actual round-trip latency value; or

wherein the controller of the first electronic device is configured to flip the second-to-least significant bit if the second-to-least significant bit of the estimated round-trip latency value is incorrect.

17 . The system according to claim 11 , wherein the controller of the first electronic device is further configured to:

generate and send, during a third period, a third test signal by the first electronic device to the second electronic device, wherein the third test signal comprises first values and second values, wherein each second value is preceded by seven first values; or

wherein the controller of the first electronic device being configured to determine if the estimated round-trip latency value is correct further comprises:

determine, based upon at least the second values of the validating signal corresponding to the sending of the second values of the third test signal, that a third-to-least significant bit of the estimated round-trip latency value is correct; or

wherein the controller of the first electronic device being configured to determine if the estimated round-trip latency value is correct determines if the estimated round-trip latency value is off by a multiple of 4 clock cycles compared to an actual round-trip latency value; or

wherein the controller of the first electronic device is further configured to flip the third-to-least significant bit if the third-to-least significant bit of the estimated round-trip latency value is incorrect.

18 . The system according to claim 11 , wherein the controller of the first electronic device is further configured to:

generate and sending, for n=1 till N, during a n-th period, a n-th test signal by the first electronic device to the second electronic device, wherein the n-th test signal comprises first and second values, wherein each second value is preceded by two to a power n minus one times a first value;

repeat the generating and sending of the test signal wherein with each repetition the value of n is increased by one; or

wherein the controller of the first electronic device being configured to determine if the estimated round trip latency value is correct determines if the estimated round trip latency value is off by a multiple of two to the power n−1 clock cycles compared to an actual round trip latency value; or

wherein the controller of the first electronic device is further configured to:

stop the repeating of the generating of the test signal based on a distance between the first electronic device and second electronic device and a speed of light.

19 . The system according to claim 11 , wherein the test signals and/or validating signals are optical signals, and wherein the first and second values are early, late or vacuum time bin qubits; or

wherein the clock signal is a Manchester encoded clock signal, and wherein the validating signal is encoded onto the clock signal; or

wherein the estimated round-trip latency value is at least partly set based on a distance between the first and second electronic device divided by a speed of light.

20 . A non-transitory computer readable medium having instructions which when executed by a quantum communication system execute a method for determining a round-trip latency of a communication channel in a quantum communication system between a first device located at a first location and a second device located at a second location that is remote from the first location, wherein the communication system comprises a clock unit configured to generate clock cycles, comprising:

setting an estimated round-trip latency value by the first device, wherein the estimated round-trip latency value is represented as a binary number and represents a latency measured in clock cycles of the clock unit;

generating and sending, during a first period, a first test signal by the first device to the second device, wherein the first test signal comprises alternating first values and second values, wherein first and second values are sent at each clock cycle of the clock unit;

saving by the first device each first and second value of the first test signal for at least a duration that corresponds to the estimated round-trip latency value,

receiving the first test signal at the second device;

sending, by the second device to the first device, upon receiving the first test signal, a validating signal that is generated by the second device and is based on the first test signal, wherein the validating signal comprises at least second values when second values from the first test signal are received;

receiving the validating signal at the first device;

comparing the validating signal with the first test signal sent during the first period; and

determining if the estimated round-trip latency value is correct based on the comparing of the validating signal and the first test signal.