Error sampler circuit

1 . An equalizer circuit, comprising:

a decision feedback equalizer (DFE) circuit having a first output and a second output;

a sign-sign least mean squares (SS-LMS) adaptation circuit having a weight value output coupled to a plurality of buffer circuits;

an error sampler circuit coupled to the DFE circuit and the SS-LMS adaptation circuit, the error sampler circuit comprising a common-mode feedback loop, and a master latch circuit, the master latch circuit including a slicer circuit; and

a slave latch circuit coupled to the master latch circuit and the SS-LMS adaptation circuit.

2 . The equalizer circuit of claim 1 , wherein the master latch circuit further comprises a first latch circuit coupled to the slicer circuit.

3 . The equalizer circuit of claim 2 , wherein the slave latch circuit comprises a comparator configured to compare a first output signal and a second output signal of the master latch circuit according to a clock signal.

4 . The equalizer circuit of claim 3 , wherein the slave latch circuit further comprises a second latch circuit coupled to the comparator, and configured to latch an output of the comparator in a first phase of the clock signal.

5 . The equalizer circuit of claim 1 , wherein the common-mode feedback loop includes:

an amplifier configured to generate an error voltage as a difference of a first common-mode voltage and a second common-mode voltage.

6 . The equalizer circuit of claim 5 , wherein the common-mode feedback loop further includes:

a buffer circuit coupled to a DAC and the amplifier.

7 . The equalizer circuit of claim 1 , wherein the common-mode feedback loop further comprises:

a first resistor and a second resistor; and

a third resistor and a fourth resistor.

8 . The equalizer circuit of claim 1 , wherein the master latch circuit includes a first latch circuit coupled to the slicer circuit, and wherein the slave latch circuit comprises:

a comparator configured to compare a first output signal and a second output signal of the master latch circuit; and

a second latch circuit coupled to the comparator.

9 . An equalizer circuit, comprising:

a decision feedback equalizer (DFE) circuit having a first output and a second output;

a sign-sign least mean squares (SS-LMS) adaptation circuit having a weight value output coupled to the DFE circuit;

an error sampler circuit coupled to the DFE circuit and the SS-LMS adaptation circuit, the error sampler circuit comprising a master latch circuit, and the master latch circuit including a slicer circuit; and

a reference voltage source, wherein the reference voltage source comprises:

a digital-to-analog converter (DAC) coupled to the SS-LMS adaptation circuit; and

a common-mode feedback loop coupled to the DAC, the DFE circuit, and the error sampler circuit.

10 . The equalizer circuit of claim 9 , wherein the common-mode feedback loop comprises:

an amplifier configured to generate an error voltage as a difference of a first common-mode voltage and a second common-mode voltage; and

a buffer circuit coupled to the DAC and the amplifier.

11 . The equalizer circuit of claim 9 , wherein the DFE circuit further comprises a plurality of data samplers and decision feedback equalizer (DFE) circuitry, wherein the DFE circuitry comprises:

a plurality of buffer circuits coupled to a summing node, wherein one of the plurality of buffer circuits is a differential amplifier coupled to a continuous time linear equalizer circuit.

12 . An equalizer circuit, comprising:

a decision feedback equalizer (DFE) circuit having a first output and a second output;

a sign-sign least mean squares (SS-LMS) adaptation circuit having a weight value output coupled to a plurality of buffer circuits;

an error sampler circuit coupled to the DFE circuit and the SS-LMS adaptation circuit, the error sampler circuit comprising a master latch circuit, and the master latch circuit including a slicer circuit; and

a slave latch circuit coupled to the master latch circuit and the SS-LMS adaptation circuit, wherein the slicer circuit is further configured to compare an input voltage to a reference voltage in a first phase of a clock signal.

13 . The equalizer circuit of claim 12 , wherein:

the input voltage comprises a first input signal and a second input signal;

the reference voltage comprises a first reference signal and a second reference signal; and

the slicer circuit comprises:

a first comparator configured to compare the first input signal and the first reference signal; and

a second comparator configured to compare the second input signal and the second reference signal.

14 . The equalizer circuit of claim 13 , further comprising a reference voltage source configured to generate the reference voltage, the reference voltage source comprising:

a digital-to-analog converter (DAC) configured to generate the reference voltage; and

a common-mode feedback loop coupled to the DAC, and configured to adjust a first common-mode voltage of the reference voltage based on a second common-mode voltage of the input voltage.

15 . The equalizer circuit of claim 14 , wherein the common-mode feedback loop comprises:

an amplifier configured to generate an error voltage as a difference of the first common-mode voltage and the second common-mode voltage; and

a buffer circuit coupled to the DAC and the amplifier, and configured to:

buffer output of the DAC;

adjust the first common-mode voltage based on the error voltage; and

provide the reference voltage to the slicer circuit.

16 . The equalizer circuit of claim 15 , wherein the common-mode feedback loop further comprises:

a first resistor and a second resistor configured to generate the second common-mode voltage; and

a third resistor and a fourth resistor configured to generate the first common-mode voltage.

17 . The equalizer circuit of claim 12 , wherein the slave latch circuit comprises a comparator configured to compare a first output signal and a second output signal of the master latch circuit in a second phase of the clock signal.

18 . The equalizer circuit of claim 17 , wherein the slave latch circuit further comprises a second latch circuit coupled to the comparator, and configured to latch an output of the comparator in the first phase of the clock signal.

19 . The equalizer circuit of claim 18 , wherein the error sample circuit includes a common-mode feedback loop.

20 . The equalizer circuit of claim 19 , wherein the common-mode feedback loop includes:

an amplifier configured to generate an error voltage as a difference of a first common-mode voltage and a second common-mode voltage.