DFE implementation for wireline applications
Disclosed embodiments include a decision feedback equalizer (DFE) comprising an N-bit parallel input adapted to be coupled to a communication channel and configured to receive consecutive communication symbols, a first DFE path including a first path input configured to receive communication symbols, and a first adder having a first adder input coupled to the first path input. There is a first DFE filter having outputs responsive to the first DFE filter inputs, the outputs coupled to the second adder input. The DFE includes a first path having a first slicer and a first multiplexer, a first path multiplexer output, and a second DFE path including a second path input configured to receive a second communication symbol, a second adder, a second DFE filter, a second slicer, and a second multiplexer.
1 . An electronic circuit comprising:
a first adder having a first input configured to receive a first symbol of a plurality of symbols;
a first filter circuit having a plurality of inputs and a plurality of outputs coupled to a plurality of second inputs of the first adder, wherein each input of the plurality of inputs is configured to have one of three values, and each output of the plurality of outputs is configured to provide an output that corresponds to a member of a set of possible combinations of the inputs of the first filter circuit;
a first slicer circuit having inputs coupled to outputs of the first adder;
a first multiplexer having inputs coupled to outputs of the first slicer circuit;
a second adder having a first input configured to receive a second symbol of the plurality of symbols;
a second filter circuit having a plurality of outputs coupled to a plurality of second inputs of the second adder, wherein each output of the plurality of outputs of the second filter circuit is configured to provide an output that corresponds to a member of a set of possible combinations of the inputs of the second filter circuit;
a second slicer circuit having inputs coupled to outputs of the second adder; and
a second multiplexer having inputs coupled to outputs of the second slicer circuit.
2 . The electronic circuit of claim 1 , wherein the first and second slicer circuits are configured to assign one of the three values to the outputs of the first and second slicer circuits responsive to the inputs of the first and second slicer circuits, respectively.
3 . The electronic circuit of claim 1 , wherein the second multiplexer includes control inputs coupled to outputs of the first multiplexer.
4 . The electronic circuit of claim 1 , wherein the inputs of the first and second filter circuits include each possible combination of outputs from the first multiplexer.
5 . The electronic circuit of claim 1 , additionally comprising:
an N-bit parallel input configured to receive the plurality of symbols transmitted at a rate of one symbol per cycle during a current clock cycle and each of previous (N−1) clock cycles, wherein N is an integer equal to or greater than 5;
a current adder having a first input configured to receive a symbol from the current clock cycle;
a current filter circuit having a plurality of outputs, wherein each output of the plurality of outputs of the current filter circuit is configured to provide an output that corresponds to a member of a set of possible combinations of the inputs of the current filter circuit;
a current multiplexer having inputs coupled to the plurality of outputs of the current filter circuit; and
a current slicer having an input coupled to an output of the current adder.
6 . The electronic circuit of claim 5 , wherein an output of the current multiplexer is coupled a second input of the current adder.
7 . The electronic circuit of claim 1 , wherein the plurality of symbols is consecutive communication symbols.
8 . The electronic circuit of claim 1 , further comprising a decision feedback equalizer (DFE) that comprises the first and second adders, the first and second slicer circuits, and the first and second multiplexers.
9 . The electronic circuit of claim 1 , further comprising an N-bit parallel input configured to receive the plurality of symbols transmitted at a rate of one symbol per cycle during a current clock cycle and each of previous (N−1) clock cycles, wherein N is an integer equal to or greater than 5.
10 . The electronic circuit of claim 1 , further comprising:
a third adder having a first input configured to receive a third symbol of the plurality of symbols;
a third filter circuit having a plurality of outputs, wherein each output of the plurality of outputs of the third filter circuit is configured to provide an output that corresponds to a member of a set of possible combinations of the inputs of the third filter circuit;
a third multiplexer having inputs coupled to the plurality of outputs of the third filter circuit, and an output coupled to a second input of the third adder; and
a third slicer having an input coupled to an output of the third adder.
11 . The electronic circuit of claim 10 , wherein the third multiplexer includes control inputs coupled to outputs of the second multiplexer.
12 . The electronic circuit of claim 11 , wherein the second multiplexer includes control inputs coupled to outputs of the first multiplexer.
13 . The electronic circuit of claim 10 , wherein the third filter circuit is a 6-tap filter.
14 . A decision feedback equalizer (DFE) comprising:
a first adder having a first input configured to receive a first symbol of a plurality of symbols;
a first filter circuit having a plurality of outputs coupled to a plurality of second inputs of the first adder;
a first slicer circuit having inputs coupled to outputs of the first adder;
a first multiplexer having inputs coupled to outputs of the first slicer circuit;
a second adder having a first input configured to receive a second symbol of the plurality of symbols;
a second filter circuit having a plurality of outputs coupled to a plurality of second inputs of the second adder;
a second slicer circuit having inputs coupled to outputs of the second adder; and
a second multiplexer having inputs coupled to outputs of the second slicer circuit, wherein the second multiplexer includes control inputs coupled to outputs of the first multiplexer.
15 . The DFE of claim 14 , further comprising:
a third adder having a first input configured to receive a third symbol of the plurality of symbols;
a third filter circuit having a plurality of outputs;
a third multiplexer having inputs coupled to the plurality of outputs of the third filter circuit, and an output coupled to a second input of the third adder; and
a third slicer having an input coupled to an output of the third adder.
16 . The DFE of claim 15 , wherein the third multiplexer includes control inputs coupled to outputs of the second multiplexer.
17 . The DFE of claim 14 , wherein the first and second slicer circuits are configured to assign one of three values to the outputs of the first and second slicer circuits responsive to the inputs of the first and second slicer circuits, respectively.
18 . The DFE of claim 14 , wherein the inputs of the first and second filter circuits include each possible combination of outputs from the first multiplexer.
19 . The DFE of claim 14 , wherein the plurality of symbols is consecutive communication symbols.