Equalization training method and apparatus, and system
An equalization training method and apparatus are described. The method includes obtaining a training rate of each of a master chip and a slave chip in a target phase of equalization training. The method also includes determining a target rate threshold interval within which the training rate in the target phase falls, determining, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configuring the target equalization timeout period as an equalization timeout period in the target phase. Accordingly, an equalization timeout period used for equalization training can be configured for each equalization training process, so that the configured equalization timeout period better conforms to a training rate currently used for link negotiation, to ensure that an equalization parameter is found within the configured equalization timeout period, improving an equalization training success rate.
1 . An equalization training method, comprising:
obtaining a training rate of each of a downstream port and an upstream port in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training; and
determining a target rate threshold interval within which the training rate in the target phase falls, determining, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configuring the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein
equalization training in the target phase is performed on the downstream port and the upstream port within the equalization timeout period in the target phase.
2 . The method according to claim 1 , wherein when the target rate threshold interval is a threshold interval comprising a minimum rate in the N+1 rate threshold intervals, the target equalization timeout period is a forward compatible equalization timeout period.
3 . The method according to claim 1 , wherein the correspondence between the N+1 rate threshold intervals and the N+1 equalization timeout periods is prestored in a register of the downstream port or in a register of the upstream port.
4 . The method according to claim 1 , wherein the downstream port and the upstream port are connected through a peripheral component interconnect express (PCIe) bus or a cache coherent interconnect for accelerators (CCIX) bus, the downstream port is a root complex or a switch chip, and the upstream port is an endpoint device independent of the downstream port.
5 . An equalization training apparatus, comprising:
a transceiver, configured to obtain a training rate of each of a downstream port and an upstream port in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training; and
at least one processor, coupled with the transceiver, configured to: determine a target rate threshold interval within which the training rate in the target phase falls, determine, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configure the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein equalization training in the target phase is performed on the downstream port and the upstream port within the equalization timeout period in the target phase.
6 . The apparatus according to claim 5 , wherein when the target rate threshold interval is a threshold interval comprising a minimum rate in the N+1 rate threshold intervals, the target equalization timeout period is a forward compatible equalization timeout period.
7 . The apparatus according to claim 5 , wherein the correspondence between the N+1 rate threshold intervals and the N+1 equalization timeout periods is prestored in a register of the downstream port or in a register of the upstream port.
8 . The apparatus according to claim 5 , wherein the downstream port and the upstream port are connected through a peripheral component interconnect express (PCIe) bus or a cache coherent interconnect for accelerators (CCIX) bus, the downstream port is a root complex or a switch chip, and the upstream port is an endpoint device independent of the downstream port.
9 . A chip, comprising:
a register, configured to store a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods;
a transceiver, configured to obtain a training rate of each of a downstream port and an upstream port in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase of phases of the equalization training; and
at least one processor, coupled with the transceiver, configured to: determine a target rate threshold interval within which the training rate in the target phase falls, determine, based on the correspondence between the N+1 rate threshold intervals and the N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configure the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein
equalization training in the target phase is performed on the downstream port and the upstream port within the equalization timeout period in the target phase.
10 . The chip according to claim 9 , wherein when the target rate threshold interval is a threshold interval comprising a minimum rate in the N+1 rate threshold intervals, the target equalization timeout period is a forward compatible equalization timeout period.
11 . The chip according to claim 9 , wherein the correspondence between the N+1 rate threshold intervals and the N+1 equalization timeout periods is prestored in a register of the downstream port or in a register of the upstream port.
12 . A communications system, comprising:
a processing system configured to execute a system software stored in a memory of the communications system;
a downstream port;
an upstream port;
wherein the downstream port and the upstream port are connected to each other through a peripheral component interconnect express (PCIe) bus or a cache coherent interconnect for accelerators (CCIX) bus; and
wherein the processing system accesses the system software in the memory and executes the system software to configure the communications system to:
obtain a training rate of each of the downstream port and the upstream port in a target phase of equalization training, wherein the target phase is a third phase or a fourth phase; and
determine a target rate threshold interval within which the training rate in the target phase falls, determine, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configure the target equalization timeout period as an equalization timeout period in the target phase, wherein N rate thresholds are predetermined, N is an integer greater than or equal to 0, and a longer rate threshold interval corresponds to a longer equalization timeout period, wherein
equalization training in the target phase is performed on the downstream port and the upstream port within the equalization timeout period in the target phase.
13 . The communications system according to claim 12 , further comprising:
the memory, configured to store the correspondence between the N+1 rate threshold intervals and the N+1 equalization timeout periods.
14 . The communications system according to claim 12 , wherein when the target rate threshold interval is a threshold interval comprising a minimum rate in the N+1 rate threshold intervals, the target equalization timeout period is a forward compatible equalization timeout period.