Pixel architecture with reduced dark current
A given pixel of a pixel array is controlled to switch between operation modes to reduce dark current during charge transfer. The charge may be transferred from a sensing node at a gate terminal of a source follower. In an example, a mode select block is used to change the power voltage level applied to a terminal of the source follower prior to or during the charge transfer process. The mode select block includes a switch coupled between a power supply terminal and the source follower transistor and a reference transistor coupled between the power supply terminal and the source follower transistor. By activating the switch in the mode select block, the power delivered to the source follower can be reduced prior to or during the charge transfer process, which can pull down the voltage at the sensing node and reduce the dark current in the pixel.
1 . An image sensor, comprising:
a plurality of pixels, wherein at least one pixel of the plurality of pixels comprises
a photodetector,
a transfer gate coupled to an output of the photodetector, and
a source follower NMOS transistor coupled to an output of the transfer gate;
a switch coupled between a power supply terminal and a drain terminal of the source follower transistor; and
an NMOS reference transistor having a drain terminal coupled to the power supply terminal and a source terminal coupled to the drain terminal of the source follower transistor,
wherein the source follower NMOS transistor operates in a saturation mode when the switch is closed, and the source follower NMOS transistor operates in a linear mode when the switch is open.
2 . The image sensor of claim 1 , wherein the transfer gate, source follower transistor, and reference transistor are all field effect transistors (FETs).
3 . The image sensor of claim 1 , further comprising a reset switch coupled between the output of the transfer gate and a reset voltage terminal.
4 . The image sensor of claim 1 , wherein a gate of the reference transistor is coupled to a reference voltage terminal.
5 . The image sensor of claim 4 , wherein the reference voltage terminal has a lower voltage compared to the power supply terminal.
6 . The image sensor of claim 1 , further comprising a pixel select switch coupled to a source terminal of the source follower transistor.
7 . An image sensor, comprising:
a pixel array having at least one column of addressable pixels;
a column amplifier coupled to the at least one column of addressable pixels;
an analog-to-digital converter (ADC) coupled to the column amplifier;
a processor coupled to the ADC; and
a mode select block;
wherein the at least one column of addressable pixels includes at least one pixel that comprises:
a photodetector,
a transfer gate coupled to an output of the photodetector, and
a source follower NMOS transistor coupled to an output of the transfer gate;
wherein the mode select block comprises:
a switch coupled between a power supply terminal and a drain terminal of the source follower transistor, and
an NMOS reference transistor having a drain terminal coupled to the power supply terminal and a source terminal coupled to the drain terminal of the source follower transistor,
wherein the source follower NMOS transistor operates in a saturation mode when the switch is closed, and the source follower NMOS transistor operates in a linear mode when the switch is open.
8 . The image sensor of claim 7 , wherein the transfer gate, source follower transistor, and reference transistor are all field effect transistors (FETs).
9 . The image sensor of claim 7 , wherein the at least one pixel further comprises a reset switch coupled between the output of the transfer gate and a reset voltage terminal.
10 . The image sensor of claim 7 , wherein a gate of the reference transistor is coupled to a reference voltage terminal.
11 . The image sensor of claim 10 , wherein the reference voltage terminal has a lower voltage compared to the power supply terminal.
12 . The image sensor of claim 7 , wherein the mode select block is coupled to each pixel of the at least one column of addressable pixels.
13 . An image sensor comprising:
a photodetector;
a transfer gate having a first terminal coupled to an output of the photodetector;
a source follower NMOS transistor having a gate terminal coupled to a second terminal of the transfer gate;
a switch having a first terminal coupled to a power supply terminal and a second terminal coupled to a drain terminal of the source follower transistor; and
an NMOS reference transistor having a drain terminal coupled to the power supply terminal, a source terminal coupled to the drain terminal of the source follower transistor, and a gate terminal coupled to a reference voltage terminal,
wherein the source follower NMOS transistor operates in a saturation mode when the switch is closed, and the source follower NMOS transistor operates in a linear mode when the switch is open.
14 . The image sensor of claim 13 , wherein the transfer gate, source follower transistor, and reference transistor are all field effect transistors (FETs).
15 . The image sensor of claim 13 , further comprising a reset switch having a first terminal coupled to a reset voltage terminal and a second terminal coupled to the second terminal of the transfer gate.
16 . The image sensor of claim 13 , wherein the reference voltage terminal has a lower voltage compared to the power supply terminal.
17 . The image sensor of claim 13 , wherein the image sensor further comprises a pixel select switch coupled to a source terminal of the source follower transistor.