Three-dimensionally structured imaging device
Provided is an imaging device that includes a first substrate including a sensor pixel that performs photoelectric conversion, a second substrate including a pixel circuit that outputs a pixel signal on a basis of electric charges outputted from the sensor pixel, and a third substrate including a processing circuit that performs signal processing on the pixel signal. The first substrate, the second substrate, and the third substrate are stacked in this order, and a low-permittivity region is provided in at least any region around a circuit that reads electric charges from the sensor pixel and outputs the pixel signal.
1 . An imaging device, comprising:
a first substrate that includes a sensor pixel, wherein the sensor pixel is configured to:
execute photoelectric conversion; and
output electric charges based on the photoelectric conversion;
a second substrate that includes a pixel circuit, wherein the pixel circuit is configured to output a pixel signal based on the electric charges;
a third substrate that includes a processing circuit, wherein
the processing circuit is configured to execute a signal processing operation on the pixel signal, and
the second substrate is on the first substrate, and the third substrate is on the second substrate; and
a low-permittivity region in a region around a specific circuit, wherein
the specific circuit reads the electric charges from the sensor pixel and outputs the pixel signal.
2 . The imaging device according to claim 1 , wherein
the sensor pixel includes:
a photoelectric conversion element;
a transfer transistor electrically coupled to the photoelectric conversion element, wherein the sensor pixel is further configured to output the electric charges from the photoelectric conversion element via the transfer transistor; and
a floating diffusion configured to temporarily hold the electric charges, and
the pixel circuit includes:
a reset transistor configured to reset a potential of the floating diffusion to a specific potential;
an amplification transistor configured to output, as the pixel signal, a signal of a voltage corresponding to a level of the electric charges that are held in the floating diffusion; and
a selection transistor configured to control an output timing of the pixel signal output from the amplification transistor.
3 . The imaging device according to claim 2 , wherein
the first substrate further includes a first semiconductor substrate,
the first semiconductor substrate includes the photoelectric conversion element, the transfer transistor, and the floating diffusion on a side of a front surface of the first semiconductor substrate,
the second substrate further includes a second semiconductor substrate,
the second semiconductor substrate includes the reset transistor, the amplification transistor, and the selection transistor on a side of a front surface of the second semiconductor substrate,
the second substrate is attached to the first substrate,
a back surface of the second semiconductor substrate is opposed to the side of the front surface of the first semiconductor substrate, based on the attachment of the second substrate to the first substrate, and
the back surface of the second semiconductor substrate is opposite to the front surface of the second semiconductor substrate.
4 . The imaging device according to claim 3 , wherein
the sensor pixel is electrically coupled to the pixel circuit by a through-wiring line,
the through-wiring line is inside a through-hole that penetrates the second semiconductor substrate, and
the low-permittivity region is in a region around the through-wiring line inside the through-hole.
5 . The imaging device according to claim 4 , wherein the through-wiring line electrically couples the floating diffusion to the amplification transistor.
6 . The imaging device according to claim 4 , wherein
the first substrate further includes:
a plurality of sensor pixels that includes the sensor pixel;
the photoelectric conversion element and the transfer transistor for each sensor pixel of the plurality of sensor pixels; and
the floating diffusion shared by each sensor pixel of the plurality of sensor pixels,
the second substrate further includes the pixel circuit for each sensor pixel of the plurality of sensor pixels, and
the through-wiring line is configured to electrically couple the floating diffusion to the amplification transistor.
7 . The imaging device according to claim 4 , wherein the low-permittivity region is in a region between the through-wiring line and the second semiconductor substrate.
8 . The imaging device according to claim 7 , wherein the low-permittivity region is in a region that surrounds the through-wiring line over an entire periphery.
9 . The imaging device according to claim 4 , wherein the low-permittivity region is in a region along an inner periphery of the through-hole.
10 . The imaging device according to claim 9 , wherein the low-permittivity region is in a region corresponding to a sidewall on an inner surface of the through-hole.
11 . The imaging device according to claim 9 , wherein
the through-hole includes a plurality of through-wiring lines, and
the plurality of through-wiring lines includes the through-wiring line.
12 . The imaging device according to claim 4 , wherein the low-permittivity region is in a region on a lateral side of at least one of the reset transistor, the amplification transistor, or the selection transistor.
13 . The imaging device according to claim 12 , wherein the low-permittivity region is at least in a region corresponding to a lateral side of the second semiconductor substrate.
14 . The imaging device according to claim 13 , wherein
the low-permittivity region is in a region surrounded by a first insulating material,
an etching rate of the first insulating material is different from an etching rate of a second insulating material, and
the second insulating material fills the through-hole.
15 . The imaging device according to claim 4 , wherein the low-permittivity region is in a region below at least one of the reset transistor, the amplification transistor, or the selection transistor.
16 . The imaging device according to claim 15 , wherein
the low-permittivity region is provided at least in a planar region, and
in a plan view of the second semiconductor substrate and in a stacking direction of the first substrate, the second substrate, and the third substrate, the amplification transistor and a gate electrode of the transfer transistor are overlapped in the planar region.
17 . The imaging device according to claim 15 , wherein the low-permittivity region is adjacent to the back surface of the second semiconductor substrate.
18 . The imaging device according to claim 4 , wherein
the low-permittivity region is in a region around a specific wiring line that is electrically coupled to the through-wiring line,
the second substrate includes a plurality of wiring lines, and
the plurality of wiring lines includes the specific wiring line.
19 . The imaging device according to claim 1 , wherein the low-permittivity region has a rectangular planar shape.
20 . The imaging device according to claim 1 , wherein the low-permittivity region comprises an air gap region.