Stackable memory module with double-sided compression contact pads
An example of an apparatus may comprise a first set of compression contact pads formed on a first side of a circuit board, a second set of compression contact pads formed on a second side of the circuit board opposite to the first side of the circuit board, where the first set of compression contact pads are respectively electrically connected to the second set of compression pads. An example of the circuit board may include a memory board. An example stackable memory module may include memory devices mounted to both sides of the memory board. Other examples are disclosed and claimed.
1 . An apparatus, comprising:
a memory board comprising:
a first plurality of compression contact pads at a first side of the memory board; and
a second plurality of compression contact pads at a second side of the memory board, the second side opposite to the first side, wherein the first plurality of compression contact pads are each electrically coupled, through the memory board, to a different respective compression contact pad of the second plurality of compression contact pads, wherein multiple microvias of the memory board are electrically coupled to each other in a stacked arrangement between one of the first plurality of compression contact pads and one of the second plurality of compression contact pads; and
two or more memory devices each coupled to the memory board independent of both the first plurality of compression contact pads and the second plurality of compression contact pads, wherein the two or more memory devices each adjoin a respective one of the first side or the second side, and wherein the two or more memory devices are further electrically coupled to the first plurality of compression contact pads.
2 . The apparatus of claim 1 , further comprising:
circuitry coupled to the two or more memory devices, the circuitry to configure the two or more memory devices to operate as a memory module.
3 . The apparatus of claim 2 , wherein the circuitry to configure the two or more memory devices to operate as the memory module comprises the circuitry is to provide any of multiple configurations of the two or more memory devices, the multiple configurations comprising:
a one memory module per channel configuration; and
a multiple memory modules per channel configuration.
4 . The apparatus of claim 3 , wherein the one memory module per channel configuration corresponds to a one dual-inline memory module per channel configuration.
5 . The apparatus of claim 3 , wherein the multiple memory modules per channel configuration corresponds to a two dual-inline memory modules per channel configuration.
6 . A method, comprising:
forming a first plurality of compression contact pads on a first side of a memory board;
forming a second plurality of compression contact pads on a second side of the memory board, wherein the second side is opposite to the first side; and
electrically coupling the first plurality of compression contact pads, through the memory board, each to a different respective compression contact pad of the second plurality of compression contact pads, the electrically coupling comprising:
forming multiple microvias which are electrically coupled to each other in a stacked arrangement between one of the first plurality of compression contact pads and one of the second plurality of compression contact pads; and
coupling two or more memory devices each to the memory board independent of both the first plurality of compression contact pads and the second plurality of compression contact pads, wherein the two or more memory devices each adjoin a respective one of the first side or the second side.
7 . The method of claim 6 , further comprising:
coupling circuitry to the memory board, wherein the circuitry is to configure the two or more memory devices to operate as a memory module.
8 . The method of claim 7 , wherein the circuitry to configure the two or more memory devices to operate as the memory module comprises the circuitry is to provide any of multiple configurations of the two or more memory devices, the multiple configurations comprising:
a one memory module per channel configuration; and
a multiple memory modules per channel configuration.
9 . The method of claim 8 , wherein the one memory module per channel configuration corresponds to a one dual-inline memory module per channel configuration.
10 . The method of claim 8 , wherein the multiple memory modules per channel configuration corresponds to a two dual-inline memory modules per channel configuration.
11 . A system, comprising:
a main board comprising a first plurality of compression contact pads at a first side of the main board;
a first memory module comprising:
a memory board comprising:
a second plurality of compression contact pads at a second side of the memory board; and
a third plurality of compression contact pads at a third side of the memory board, the third side opposite to the second side, wherein the second plurality of compression contact pads are each electrically coupled, through the memory board, to a different respective compression contact pad of the third plurality of compression contact pads, and wherein multiple microvias of the memory board are electrically coupled to each other in a stacked arrangement between one of the second plurality of compression contact pads and one of the third plurality of compression contact pads; and
two or more memory devices each coupled to the memory board independent of both the second plurality of compression contact pads and the third plurality of compression contact pads, wherein the two or more memory devices each adjoin a respective one of the second side or the third side, and wherein the two or more memory devices are further electrically coupled to the first plurality of compression contact pads; and
a first compression mount connector compressed between the main board and the first memory module to communicatively couple the first plurality of compression contact pads to the second plurality of compression contact pads.
12 . The system of claim 11 , further comprising:
circuitry to provide any of multiple configurations of the first memory module, the multiple configurations comprising:
a one memory module per channel configuration; and
a multiple memory modules per channel configuration.
13 . The system of claim 12 , wherein the one memory module per channel configuration corresponds to a one dual-inline memory module per channel configuration.
14 . The system of claim 11 , wherein:
the main board further comprises a fourth plurality of compression contact pads at a fourth side of the main board, wherein the fourth side is opposite to the first side; and
the system further comprises:
a second memory module comprising a fifth plurality of compression contact pads at a fifth side of the second memory module; and
a second compression mount connector compressed between the main board and the second memory module to communicatively couple the fifth plurality of compression contact pads and the fourth plurality of compression contact pads.
15 . The system of claim 11 , further comprising:
a second memory module comprising a fourth plurality of compression contact pads at a fourth side of the second memory module; and
a second compression mount connector compressed between the first memory module and the second memory module to communicatively couple the fourth plurality of compression contact pads to the third plurality of compression contact pads.
16 . The system of claim 15 , wherein the second memory module further comprises a fifth plurality of compression contact pads at a fifth side of the second memory module, wherein the fifth side is opposite the fourth side.
17 . The system of claim 11 , wherein, for each microvia of the multiple microvias, a respective plated conductor is formed on a top of the microvia.