Static random access memory with pre-charge circuit
The present disclosure describes embodiments of a memory device with a pre-charge circuit. The memory device can include a memory cell, and the pre-charge circuit can include a first transistor and a second transistor. The first transistor includes a first gate terminal, a first source/drain (S/D) terminal coupled to a reference voltage, and a second S/D terminal coupled to a first terminal of the memory cell. The second transistor includes a second gate terminal, a third S/D terminal coupled to the reference voltage, and a fourth S/D terminal coupled to the second terminal of the memory cell. The first and second transistors are configured to pass the reference voltage in response to the control signal being applied to the first and second gate terminals, respectively.
1 . A device, comprising:
a memory cell electrically coupled to a first bitline and to a second bitline;
a first transistor with a first gate terminal coupled to a control signal, a first source/drain (S/D) terminal coupled to a power supply voltage, and a second S/D terminal, wherein the first transistor is configured to pass the power supply voltage from the first S/D terminal to the second S/D terminal in response to the control signal transitioning from a first value to a second value at the first gate terminal;
a second transistor with a second gate terminal coupled to the control signal, a third S/D terminal coupled to the power supply voltage, and a fourth S/D terminal, wherein the second transistor is configured to pass the power supply voltage from the third S/D terminal to the fourth S/D terminal in response to the control signal transitioning from the first value to the second value at the second gate terminal;
a first pass transistor with a third gate terminal coupled to the control signal, a fifth S/D terminal connected to the second S/D terminal, and a sixth S/D terminal connected to the first bitline, wherein the first pass transistor is configured to pass the power supply voltage from the first transistor to the first bitline in response to the control signal transitioning from the first value to the second value at the third gate terminal; and
a second pass transistor with a fourth gate terminal coupled to the control signal, a seventh S/D terminal connected to the fourth S/D terminal, and an eighth S/D terminal connected to the second bitline, wherein the second pass transistor is configured to pass the power supply voltage from the second transistor to the second bitline in response to the control signal transitioning from the first value to the second value at the fourth gate terminal, and wherein the first transistor, the second transistor, the first pass transistor, and the second pass transistor are the same type of transistor.
2 . The device of claim 1 , further comprising:
a third transistor with a fifth gate terminal coupled to the control signal, a ninth S/D terminal coupled to a reference voltage, and a tenth S/D terminal connected to the second S/D terminal, wherein the third transistor is configured to pass the reference voltage from the ninth S/D terminal to the first pass transistor in response to the control signal transitioning from the second value to the first value.
3 . The device of claim 2 , further comprising:
a fourth transistor with a sixth gate terminal connected to the second gate terminal coupled to the control signal, an eleventh S/D terminal coupled to the reference voltage, and a twelfth S/D terminal connected to the fourth S/D terminal, wherein the fourth transistor is configured to pass the reference voltage from the eleventh S/D terminal to the second pass transistor in response to the control signal transitioning from the second value to the first value.
4 . The device of claim 3 , wherein:
the first transistor, the first pass transistor, the second transistor, and the second pass transistor are p-type field effect transistors; and
the third transistor and the fourth transistor are n-type field effect transistors.
5 . The device of claim 1 , wherein:
the first pass transistor is a p-type field effect transistor; and
the second pass transistor is an other p-type field effect transistor.
6 . The device of claim 1 , wherein the first transistor, the first pass transistor, the second transistor, and the second pass transistor are n-type field effect transistors.
7 . The device of claim 1 , wherein the first transistor, the first pass transistor, the second transistor, and the second pass transistor are p-type field effect transistors.
8 . The device of claim 1 , wherein the first and second transistors are p-type field effect transistors.
9 . The device of claim 1 , wherein the first and second transistors are n-type field effect transistors.
10 . A memory device, comprising:
a memory cell comprising a first bitline node and a second bitline node;
a first transistor device coupled to a power supply voltage and comprising:
a first gate terminal configured to activate the first transistor device based on a control signal transitioning from a first value to a second value; and
a first source/drain (S/D) terminal configured to receive the power supply voltage based on the control signal transitioning from the first value to the second value at the first gate terminal;
a second transistor device coupled to the power supply voltage and comprising:
a second gate terminal connected to the first gate terminal and configured to activate the second transistor device based on the control signal transitioning from the first value to the second value; and
a second S/D terminal configured to receive the power supply voltage based on the control signal transitioning from the first value to the second value at the second gate terminal;
a first pass device connected to the first transistor device and the memory cell, wherein the first pass device comprises:
a third S/D terminal connected to the first bitline node; and
a third gate terminal configured to activate the first pass device to pass the power supply voltage from the first S/D terminal of the first transistor device to the third S/D terminal and the first bitline node based on the control signal transitioning from the first value to the second value at the third gate terminal; and
a second pass device connected to the second transistor device and the memory cell, wherein the second pass device comprises:
a fourth S/D terminal connected to the second bitline node; and
a fourth gate terminal configured to activate the second pass device to pass the power supply voltage from the second S/D terminal of the second transistor device to the fourth S/D terminal to the second bitline node based on the control signal transitioning from the first value to the second value at the fourth gate terminal, wherein the first gate terminal, the second gate terminal, the third gate terminal, and the fourth gate terminal are connected to the control signal.
11 . The memory device of claim 10 , wherein:
the first transistor device is configured to pass the power supply voltage to the first pass device in response to the control signal being applied to the first gate terminal of the first transistor device; and
the second transistor device is configured to pass the power supply voltage to the second pass device in response to the control signal being applied to second gate terminal of the second transistor device.
12 . The memory device of claim 11 , further comprising:
a third transistor device configured to pass a reference voltage to the first pass device in response to the control signal transitioning from the second value to the first value; and
a fourth transistor device configured to pass the reference voltage to the second pass device in response to the control signal transitioning from the second value to the first value.
13 . The memory device of claim 12 , wherein:
the first pass device, the second pass device, the first transistor device, and the second transistor device are p-type field effect transistors; and
the third transistor device the fourth transistor device are n-type field effect transistors.
14 . The memory device of claim 10 , wherein the first pass device, the second pass device, the first transistor device, and the second transistor device are n-type field effect transistors.
15 . The memory device of claim 10 , further comprising:
a third transistor device configured to pass a reference voltage to the first pass device; and
a fourth transistor device configured to pass the reference voltage to the second pass device.
16 . The memory device of claim 15 , wherein the first pass device, the second pass device, the third transistor device, and the fourth transistor device are n-type field effect transistors.
17 . A memory system, comprising:
a memory array comprising a memory cell with a first bitline node and a second bitline node; and
a pre-charge circuit coupled to the memory array and comprising:
a first transistor device coupled to a power supply voltage and comprising a first gate terminal configured to receive a control signal that transitions from a first value to a second value at the first gate terminal;
a second transistor device coupled to the power supply voltage and comprising a second gate terminal configured to receive the control signal that transitions from the first value to the second value at the second gate terminal;
a first pass device comprising a third gate terminal configured to cause the first pass device to pass the power supply voltage from the first transistor device to the first bitline node based on the control signal transitioning from the first value to the second value at the third gate terminal; and
a second pass device comprising a fourth gate terminal configured to cause the second pass device to pass the power supply voltage from the second transistor device to the second bitline node based on the control signal transitioning from the first value to the second value at the fourth gate terminal, wherein the first transistor device, the second transistor device, the first pass device, and the second pass device are the same type of transistor, and wherein the first gate terminal, the second gate terminal, the third gate terminal, and the fourth gate terminal are connected to the control signal.
18 . The memory system of claim 17 , wherein:
the first transistor device is configured to pass the power supply voltage to the first pass device in response to the control signal being applied to the first gate terminal of the first transistor device; and
the second transistor device is configured to pass the power supply voltage to the second pass device in response to the control signal being applied to the second gate terminal of the second transistor device.
19 . The memory system of claim 18 , wherein the pre-charge circuit further comprises:
a third transistor device configured to pass a reference voltage to the first pass device in response to the control signal being applied to a fifth gate terminal of the third transistor device; and
a fourth transistor device configured to pass the reference voltage to the second pass device in response to the control signal being applied to a sixth gate terminal of the fourth transistor device.
20 . The memory system of claim 17 , wherein the pre-charge circuit further comprises:
a third transistor device configured to pass a reference voltage to the first pass device; and
a fourth transistor device configured to pass the reference voltage to the second pass device.