Static random access memory and manufacturing method thereof
View Patent ↗A static random access memory and a manufacturing method thereof are provided. The static random access memory includes a first complementary field effect transistor (CFET), a second CFET, a first pass fate transistor and a second pass gate transistor. The first CFET and the second CFET are disposed in a first tier. The first pass gate transistor is connected to the first CFET through a first path. The second pass gate transistor is connected to the second CFET through a second path. The first pass gate transistor and the second pass gate transistor are disposed in a second tier.
1 . A static random access memory, comprising:
a first complementary field effect transistor (CFET); and
a second CFET, wherein the first CFET and the second CFET are disposed in a first tier;
a first pass gate transistor, connected to the first CFET through a first path; and
a second pass gate transistor, connected to the second CFET through a second path, wherein the first pass gate transistor and the second pass gate transistor are disposed in a second tier;
wherein in a plan view of the static random access memory, the first CFET is extended along an arrange line, the second CFET is extended along the arrange line, and the first path and the second path are located at different sides of the arrange line.
2 . The static random access memory according to claim 1 , wherein the first pass gate transistor and the second pass gate transistor share one gate.
3 . The static random access memory according to claim 2 , wherein the first pass gate transistor includes a first channel layer, the second pass gate transistor includes a second channel layer, and the first channel layer and the second channel layer are located on a dielectric layer covering the first CFET and the second CFET.
4 . The static random access memory according to claim 3 , wherein the gate is located above the first channel layer and the second channel layer.
5 . The static random access memory according to claim 3 , wherein the gate is located below the first channel layer and the second channel layer.
6 . The static random access memory according to claim 3 , wherein the first channel layer and the second channel layer are embedded in the gate.
7 . The static random access memory according to claim 1 , wherein the first path and the second path are vias.
8 . The static random access memory according to claim 1 , wherein the first pass gate transistor is connected to a first bit line by a via, and the second pass gate transistor is connected to a second bit line by a via.
9 . The static random access memory according to claim 1 , wherein in the first tier, the first CFET and the second CFET are located in the same column.
10 . The static random access memory according to claim 1 , wherein in the second tier, the first pass gate transistor and the second pass gate transistor are located in the same column.
11 . A static random access memory, comprising:
a first complementary field effect transistor (CFET);
a second CFET, wherein the first CFET and the second CFET are disposed in a first tier, an output of the first CFET is connected to an input of the second CFET through a first path, an input of the first CFET is connected to an output of the second CFET through a second path;
a first pass gate transistor, connected to the first CFET and located above the first CFET; and
a second pass gate transistor, connected to the second CFET and located above the second CFET, wherein the first pass gate transistor and the second gate transistor are disposed in a second tier;
wherein in a plan view of the static random access memory, the first CFET is extended along an arrange line, the second CFET is extended along the arrange line, and the first path and the second path are located at different sides of the arrange line.
12 . The static random access memory according to claim 11 , wherein the first pass gate transistor and the second pass gate transistor share one gate.
13 . The static random access memory according to claim 12 , wherein the first pass gate transistor includes a first channel layer, the second pass gate transistor includes a second channel layer, and the first channel layer and the second channel layer are located on a dielectric layer covering the first CFET and the second CFET.
14 . The static random access memory according to claim 13 , wherein the gate is located below the first channel layer and the second channel layer.
15 . The static random access memory according to claim 13 , wherein the first channel layer and the second channel layer are embedded in the gate.
16 . The static random access memory according to claim 11 , wherein the first path and the second path are vias.
17 . The static random access memory according to claim 11 , wherein the first pass gate transistor is connected to a first bit line by a via, and the second pass gate transistor is connected to a second bit line by a via.
18 . The static random access memory according to claim 11 , wherein in the first tier, the first CFET and the second CFET are located in the same column.
19 . The static random access memory according to claim 11 , wherein in the second tier, the first pass gate transistor and the second pass gate transistor are located in the same column.
20 . A static random access memory, comprising:
a first complementary field effect transistor (CFET); and
a second CFET, wherein the first CFET and the second CFET are disposed in a first tier, an output of the first CFET is connected to an input of the second CFET through a first path, an input of the first CFET is connected to an output of the second CFET through a second path;
wherein in a plan view of the static random access memory, the first CFET is extended along an arrange line, the second CFET is extended along the arrange line, and the first path and the second path are located at different sides of the arrange line.