IP Library › Granted Patent US 12707622
Granted Patent B2
US 12707622 · App. 18/522,663 · Granted Aug 11, 2026

Semiconductor device

Inventors: Jee Woong Kim (Suwon-si, KR); Kyung Hee Cho (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H10B10/125
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Quick Facts
Patent No.
US 12707622
App. No.
18/522,663
Granted
Aug 11, 2026
Kind
B2
Abstract

A semiconductor device includes a first lower active pattern and a second lower active pattern, a first upper active pattern and a second upper active pattern, a first gate electrode that overlaps the first lower active pattern and the first upper active pattern, a second gate electrode spaced apart from the first gate electrode, a third gate electrode spaced apart from the first gate electrode, a fourth gate electrode spaced apart from the third gate electrode, a first lower source/drain contact that is electrically connected to the first lower active pattern, a first upper source/drain contact that is electrically connected to the second upper active pattern, a lower shared contact in the lower region, and an upper shared contact in the upper region.

Claims (72)

1 . A semiconductor device comprising a lower region and an upper region on a substrate, the semiconductor device comprising:

a first lower active pattern and a second lower active pattern that extend in a first direction, extend in the lower region, and are spaced apart from each other in a second direction that intersects the first direction;

a first upper active pattern and a second upper active pattern that extend in the first direction, extend in the upper region, and are spaced apart from each other in the second direction;

a first gate electrode that overlaps the first lower active pattern and the first upper active pattern;

a second gate electrode spaced apart from the first gate electrode in the second direction, wherein the second gate electrode overlaps at least one of the second lower active pattern and the second upper active pattern;

a third gate electrode spaced apart from the first gate electrode in the first direction, wherein the third gate electrode overlaps at least one of the first lower active pattern and the first upper active pattern;

a fourth gate electrode spaced apart from the third gate electrode in the second direction, wherein the fourth gate electrode overlaps the second lower active pattern and the second upper active pattern;

a first lower source/drain contact that is electrically connected to the first lower active pattern and is between the first gate electrode and the third gate electrode;

a first upper source/drain contact that is electrically connected to the second upper active pattern and is between the second gate electrode and the fourth gate electrode;

a lower shared contact in the lower region, wherein the lower shared contact is electrically connected to the first lower source/drain contact and the fourth gate electrode; and

an upper shared contact in the upper region, wherein the upper shared contact is electrically connected to the first upper source/drain contact and the first gate electrode.

2 . The semiconductor device of claim 1 , wherein the lower shared contact extends from a side surface of the first lower source/drain contact and is electrically connected to a side surface of the fourth gate electrode.

3 . The semiconductor device of claim 2 , wherein the lower shared contact extends in the first direction.

4 . The semiconductor device of claim 1 , wherein the upper shared contact is on an upper surface of the first upper source/drain contact and an upper surface of the first gate electrode.

5 . The semiconductor device of claim 4 , wherein the lower shared contact extends in the first direction.

6 . The semiconductor device of claim 1 , further comprising a cutting pattern that extends in the first direction, separates the first gate electrode and the second gate electrode, and separates the third gate electrode and the fourth gate electrode.

7 . The semiconductor device of claim 6 , wherein a length of the first gate electrode in the second direction is the same as a length of the third gate electrode in the second direction, and

a length of the second gate electrode in the second direction is the same as a length of the fourth gate electrode in the second direction.

8 . The semiconductor device of claim 1 , further comprising:

a second upper source/drain contact that is electrically connected to the first upper active pattern and is between the first gate electrode and the third gate electrode; and

a second lower source/drain contact that is electrically connected to the second lower active pattern and is between the second gate electrode and the fourth gate electrode,

wherein the first lower source/drain contact is electrically connected to the second upper source/drain contact, and

the first upper source/drain contact is electrically connected to the second lower source/drain contact.

9 . A semiconductor device comprising a lower region and an upper region on a substrate, the semiconductor device comprising:

a first lower active pattern and a second lower active pattern that extend in a first direction, extend in the lower region, and are spaced apart from each other in a second direction that intersects the first direction;

a first upper active pattern and a second upper active pattern that extend in the first direction, extend in the upper region, and are spaced apart from each other in the second direction;

a first gate electrode that overlaps the first lower active pattern and the first upper active pattern;

a second gate electrode that overlaps the second lower active pattern and the second upper active pattern, wherein the second gate electrode does not overlap the first gate electrode in the second direction;

a first lower source/drain contact that is electrically connected to the first lower active pattern and is between the first gate electrode and the second gate electrode;

a first upper source/drain contact that is electrically connected to the first upper active pattern and on the first lower source/drain contact;

a second lower source/drain contact that is spaced apart from the first lower source/drain contact in the second direction and is electrically connected to the second lower active pattern;

a second upper source/drain contact spaced apart from the first upper source/drain contact in the second direction and electrically connected to the second upper active pattern;

a lower shared contact in the lower region, wherein the lower shared contact is electrically connected to the first lower source/drain contact and the second gate electrode; and

an upper shared contact in the upper region, wherein the upper shared contact is electrically connected to the second upper source/drain contact and the first gate electrode.

10 . The semiconductor device of claim 9 , wherein the first lower source/drain contact is electrically connected to the first upper source/drain contact, and

the second lower source/drain contact is electrically connected to the second upper source/drain contact.

11 . The semiconductor device of claim 9 , wherein a length of the first lower source/drain contact in the second direction is greater than a length of the second lower source/drain contact in the second direction.

12 . The semiconductor device of claim 9 , wherein a length of the second upper source/drain contact in the second direction is greater than a length of the first upper source/drain contact in the second direction.

13 . The semiconductor device of claim 9 , further comprising:

a third lower source/drain contact, wherein the first gate electrode is between the first lower source/drain contact and the third lower source/drain contact, and wherein the third lower source/drain contact is electrically connected to the first lower active pattern; and

a third upper source/drain contact that is on the third lower source/drain contact and is electrically connected to the first upper active pattern,

wherein the third lower source/drain contact is configured to receive a first signal comprising a first voltage, and

the third upper source/drain contact is configured to receive a second signal comprising a second voltage.

14 . The semiconductor device of claim 13 , further comprising:

a fourth lower source/drain contact, wherein the second gate electrode is between the second lower source/drain contact and the fourth lower source/drain contact, and wherein the fourth lower source/drain contact is electrically connected to the second lower active pattern; and

a fourth upper source/drain contact that is on the fourth lower source/drain contact and is electrically connected to the second upper active pattern,

wherein the fourth lower source/drain contact is configured to receive the first signal, and

the fourth upper source/drain contact is configured to receive the second signal.

15 . A semiconductor device comprising:

a substrate;

a first active pattern comprising a first lower active pattern and a first upper active pattern that are on the substrate, are spaced apart from each other, and extend in a first direction;

a second active pattern comprising a second lower active pattern and a second upper active pattern that are on the substrate, spaced apart from each other, and extend in the first direction, wherein the second active pattern is spaced apart from the first active pattern in a second direction that intersects the first direction;

a cutting pattern that extends in the first direction and is between the first active pattern and the second active pattern;

a first gate structure that extends in the second direction, the first gate structure comprising a first gate electrode that overlaps the first active pattern and a second gate electrode that overlaps the second active pattern, wherein the first gate electrode and the second gate electrode are separated by the cutting pattern;

a second gate structure that is spaced apart from the first gate structure and extends in the second direction, the second gate structure comprising a third gate electrode that overlaps the first active pattern and a fourth gate electrode that overlaps the second active pattern, wherein the third gate electrode and the fourth gate electrode are separated by the cutting pattern;

a first lower source/drain contact that is electrically connected to the first lower active pattern and is between the first gate electrode and the third gate electrode;

a first upper source/drain contact that is electrically connected to the first lower source/drain contact and the first upper active pattern and is on the first lower source/drain contact;

a second lower source/drain contact that is electrically connected to the second lower active pattern and is between the second gate electrode and the fourth gate electrode;

a second upper source/drain contact that is electrically connected to the second lower source/drain contact and the second upper active pattern and is on the second lower source/drain contact;

a lower shared contact that extends in the first direction and is electrically connected to the first lower source/drain contact and the fourth gate electrode; and

an upper shared contact that extends in the first direction and is electrically connected to the second upper source/drain contact and the first gate electrode.

16 . The semiconductor device of claim 15 , wherein a first distance between an upper surface of the lower shared contact and an upper surface of the substrate is less than a second distance between a lower surface of the second upper source/drain contact and the upper surface of the substrate.

17 . The semiconductor device of claim 15 , wherein a first distance between a lower surface of the upper shared contact and an upper surface of the substrate is greater than a second distance between an upper surface of the first lower source/drain contact and the upper surface of the substrate.

18 . The semiconductor device of claim 15 , wherein at least a portion of the lower shared contact overlaps the cutting pattern in a third direction that intersects an upper surface of the substrate.

19 . The semiconductor device of claim 15 , wherein the upper shared contact does not overlap the cutting pattern in a third direction that intersects an upper surface of the substrate.

20 . The semiconductor device of claim 15 , further comprising:

a third lower source/drain contact, wherein the first gate electrode is between the first lower source/drain contact and the third lower source/drain contact, and wherein the third lower source/drain contact is electrically connected to the first lower active pattern;

a third upper source/drain contact that is electrically connected to the first upper active pattern and is on the third lower source/drain contact;

a fourth lower source/drain contact, wherein the fourth gate electrode is between the second lower source/drain contact and the fourth lower source/drain contact, and wherein the fourth lower source/drain contact is electrically connected to the second lower active pattern; and

a fourth upper source/drain contact that is electrically connected to the second upper active pattern and is on the fourth lower source/drain contact,

wherein the third lower source/drain contact and the fourth lower source/drain contact are configured to receive a first signal comprising a first voltage, and

wherein the third upper source/drain contact and the fourth upper source/drain contact are configured to receive a second signal comprising a second voltage.