Semiconductor device structure
A semiconductor device structure is provided. The semiconductor device structure includes a first device formed over a substrate, and the first device comprises a first channel structure. The semiconductor device structure includes a first gate stack wrapped around the first channel structure, and a second device formed over the first device. The second device comprises a plurality of second nanostructures stacked in a vertical direction. The semiconductor device structure include a second gate stack wrapped around the second nanostructures, and a portion of the first gate stack is higher than a topmost second nanostructure.
1 . A semiconductor device structure, comprising:
a first device formed over a substrate, wherein the first device comprises a first channel structure;
a first gate stack wrapped around the first channel structure;
a second device formed over the first device, wherein the second device comprises a plurality of second nanostructures stacked in a vertical direction; and
a second gate stack wrapped around the second nanostructures, wherein a portion of the first gate stack is higher than a topmost second nanostructure,
wherein a number of the first channel structure and a number of the second nanostructures are different.
2 . The semiconductor device structure as claimed in claim 1 , further comprising:
a first S/D structure formed over the first channel structure; and
a second S/D structure formed over the second nanostructures, wherein the second S/D structure is directly above the first S/D structure.
3 . The semiconductor device structure as claimed in claim 2 , further comprising:
a first contact formed on the first S/D structure; and
a second contact formed on the second S/D structure, wherein a portion of the first contact is higher than a bottom surface of the second contact.
4 . The semiconductor device structure as claimed in claim 1 , further comprising:
a first inner gate spacer between the first gate stack and the second gate stack, wherein a longitude of the first inner gate spacer is along a vertical direction, and the first inner gate spacer has a first sidewall surface in direct contact with the first gate stack and a second sidewall surface in direct contact with the second gate stack.
5 . The semiconductor device structure as claimed in claim 4 , wherein the first gate stack has a first height, the first inner gate spacer has a second height, and the first height is greater than the second height.
6 . The semiconductor device structure as claimed in claim 4 , wherein the first inner gate spacer has a bottom surface in direct contact with the first gate stack.
7 . The semiconductor device structure as claimed in claim 1 , further comprising:
a second inner gate spacer below and in direct contact with the first channel structure.
8 . The semiconductor device structure as claimed in claim 1 , wherein one of the first device and the second device is a logic circuit device, and the other is a static random access memory (SRAM).
9 . The semiconductor device structure as claimed in claim 1 , wherein a top surface of the first gate stack is substantially coplanar with a top surface of the second gate stack.
10 . A semiconductor device structure, comprising:
a first device formed over a substrate, wherein the first device comprises a first channel structure;
a first gate stack wrapped around the first channel structure, wherein the first gate stack comprises a first gate dielectric layer formed on a sidewall surface of the first channel structure,
and the first gate dielectric layer has a first height along a vertical direction;
a first S/D structure formed adjacent to the first gate stack;
a first S/D contact structure formed on the first S/D structure;
a second device formed over the first device, wherein the second device comprises a plurality of second nanostructures stacked in a vertical direction;
a second gate stack wrapped around the second nanostructures, wherein the second gate stack comprises a second gate dielectric layer formed on a sidewall surface of one of the second nanostructures, wherein the second gate dielectric layer has a second height along the vertical direction, and the first height is different from the second height;
a second S/D structure formed adjacent to the first gate stack; and
a second S/D contact structure formed on the second S/D structure, wherein a portion of the first S/D contact structure is higher than a bottom surface of the second S/D contact structure.
11 . The semiconductor device structure as claimed in claim 10 , further comprising:
a first metal silicide layer surrounding the first S/D structure; and
the first S/D contact structure surrounding the first metal silicide layer, wherein a portion of the first S/D contact structure is directly below the first S/D structure.
12 . The semiconductor device structure as claimed in claim 10 , further comprising:
a contact spacer formed between the first S/D contact structure and the second S/D contact structure, wherein a bottommost surface of the contact spacer is lower than a bottommost surface of the second S/D contact structure.
13 . The semiconductor device structure as claimed in claim 12 , further comprising:
an etch stop layer between the first S/D structure and the second S/D structure, wherein the etch stop layer is in direct contact with contact spacer.
14 . The semiconductor device structure as claimed in claim 12 , further comprising:
a gate spacer formed on a sidewall surface of the first gate stack, wherein a bottom surface of the gate spacer is lower than the bottommost surface of the contact spacer.
15 . A semiconductor device structure, comprising:
a plurality of first nanostructures formed over a substrate, wherein the first nanostructures are stacked in a vertical direction;
a first gate stack wrapped around the first nanostructures;
a first inner gate spacer formed over the first nanostructures;
a second channel structure formed over the first inner gate spacer; and
a second gate stack wrapped around the second channel structure, wherein the second channel structure is separated from the first inner gate spacer by the second gate stack, and a height of one of the first nanostructures is smaller than a height of the second channel structure.
16 . The semiconductor device structure as claimed in claim 15 , further comprising:
a gate spacer layer formed on a sidewall surface of the first gate stack, wherein a bottom surface of the gate spacer layer is lower than a bottom surface of the second gate stack.
17 . The semiconductor device structure as claimed in claim 15 , further comprising:
a second inner gate spacer between the first gate stack and the second gate stack, wherein the second inner gate spacer is formed along a vertical direction, and a portion of the first gate stack is directly below the second inner gate spacer.
18 . The semiconductor device structure as claimed in claim 15 , wherein a top surface of the first gate stack is substantially coplanar with a top surface of the second gate stack.
19 . The semiconductor device structure as claimed in claim 15 , wherein a bottommost surface of the second gate stack is higher than a bottommost surface of the first gate stack.
20 . The semiconductor device structure as claimed in claim 15 , further comprising:
a first S/D structure formed adjacent to the first gate stack;
a first S/D contact formed on the first S/D structure;
a second S/D structure formed adjacent to the second gate stack; and
a second S/D contact formed on the second S/D structure, wherein a portion of the first S/D contact is higher than a bottom surface of the second S/D contact.