Method for forming memory device

1 . A method, comprising:

forming a metal-insulator-semiconductor (MIS) structure, wherein the MIS structure comprises:

a semiconductor layer;

an insulating layer over the semiconductor layer; and

a metal electrode layer over the insulating layer;

performing a soft breakdown process to the MIS structure to form a local breakdown portion in the insulating layer;

performing a first write operation by supplying a first voltage pulse to the metal electrode layer;

performing a first read operation by supplying a second voltage pulse to the metal electrode layer and detecting a first read current flowing through the MIS structure;

performing a second write operation by supplying a third voltage pulse to the metal electrode layer, wherein the first voltage pulse has a higher voltage level than the third voltage pulse; and

performing a second read operation by supplying a fourth voltage pulse to the metal electrode layer and detecting a second read current flowing through the MIS structure, wherein the first read current is different from the second read current, and wherein the third voltage pulse has a lower voltage level than the second and fourth voltage pulses.

2 . The method of claim 1 , wherein the soft breakdown process comprises supplying a voltage to the metal electrode layer, such that the semiconductor layer is under deep depletion regime during performing the soft breakdown process.

3 . The method of claim 2 , wherein the voltage gradually increases during the soft breakdown process.

4 . The method of claim 2 , wherein the soft breakdown process further comprises setting a maximum current flowing through the MIS structure.

5 . The method of claim 1 , wherein the soft breakdown process comprises supplying a forward bias to the metal electrode layer, such that the semiconductor layer is under accumulation regime during performing the soft breakdown process.

6 . The method of claim 1 , wherein the semiconductor layer is a p-type semiconductor layer, and the soft breakdown process comprises supplying a positive voltage to the metal electrode layer.

7 . The method of claim 1 , wherein the semiconductor layer is an n-type semiconductor layer, and the soft breakdown process comprises supplying a negative voltage to the metal electrode layer.

8 . The method of claim 1 , wherein the soft breakdown process comprises supplying a constant current to the metal electrode layer.

9 . The method of claim 1 , wherein the soft breakdown process comprises supplying a gradually increasing current to the metal electrode layer.

10 . The method of claim 1 , wherein the local breakdown portion extends downward from an interface between the metal electrode layer and the insulating layer and terminates prior to reaching an interface between the semiconductor layer and the insulating layer.

11 . A method, comprising:

forming an insulating layer over a semiconductor layer;

forming a metal electrode layer over the insulating layer, wherein the semiconductor layer, the insulating layer, and the metal electrode layer serve as a metal-insulator-semiconductor (MIS) structure;

transferring the MIS structure to a MIS memory structure, comprising:

supplying a voltage to the metal electrode layer, such that the MIS structure is under reverse bias and the semiconductor layer is under deep depletion regime; and

stop supplying the voltage to the metal electrode layer until a local breakdown portion is formed in the insulating layer;

performing a first write operation to the MIS memory structure by supplying a first voltage pulse to the metal electrode layer;

performing a first read operation to the MIS memory structure by supplying a second voltage pulse to the metal electrode layer and detecting a first read current flowing through the MIS structure;

performing a second write operation to the MIS memory structure by supplying a third voltage pulse to the metal electrode layer, wherein the first voltage pulse has a higher voltage level than the third voltage pulse; and

performing a second read operation to the MIS memory structure by supplying a fourth voltage pulse to the metal electrode layer and detecting a second read current flowing through the MIS structure, wherein the first read current is different from the second read current, and wherein the third voltage pulse has a lower voltage level than the second and fourth voltage pulses.

12 . The method of claim 11 , wherein the first read current is about two orders of magnitude the second read current.

13 . The method of claim 11 , further comprising etching the semiconductor layer to form a fin structure protruding over the semiconductor layer, wherein the insulating layer is formed lining the fin structure and the semiconductor layer, and wherein the local breakdown portion is formed in a portion of the insulating layer lining the fin structure.

14 . The method of claim 11 , further comprising etching the semiconductor layer to form a recess in the semiconductor layer, wherein the insulating layer is formed lining the recess and a top surface of the semiconductor layer, and wherein the local breakdown portion is formed in a portion of the insulating layer lining the recess.

15 . The method of claim 11 , wherein the local breakdown portion extends downward from an interface between the metal electrode layer and the insulating layer and terminates prior to reaching an interface between the semiconductor layer and the insulating layer.

16 . A method, comprising:

etching a semiconductor layer to form a fin structure protruding over the semiconductor layer;

forming an insulating layer over the semiconductor layer and lining the fin structure;

forming first and second metal electrode layers in contact with the insulating layer, wherein the first metal electrode layer, the insulating layer, and the fin structure serve as a first metal-insulator-semiconductor (MIS) structure, and the second metal electrode layer, the insulating layer, and the fin structure serve as a second metal-insulator-semiconductor (MIS) structure;

transferring the first MIS structure to a first MIS memory structure by supplying a first voltage to the first metal electrode layer until a first local breakdown portion is formed in the insulating layer;

transferring the second MIS structure to a second MIS memory structure by supplying a second voltage to the second metal electrode layer until a second local breakdown portion is formed in the insulating layer;

performing a first write operation by supplying a first voltage pulse to the first metal electrode layer;

performing a first read operation by supplying a second voltage pulse to the first metal electrode layer and detecting a first read current flowing through the first MIS structure;

performing a second write operation by supplying a third voltage pulse to the first metal electrode layer, wherein the first voltage pulse has a higher voltage level than the third voltage pulse; and

performing a second read operation by supplying a fourth voltage pulse to the first metal electrode layer and detecting a second read current flowing through the first MIS structure, wherein the first read current is different from the second read current, and wherein the third voltage pulse has a lower voltage level than the second and fourth voltage pulses.

17 . The method of claim 16 , further comprising forming a dielectric layer vertically separating the first and second metal electrode layers.

18 . The method of claim 16 , wherein the first and second metal electrode layers are on opposite sides of the fin structure.

19 . The method of claim 16 , wherein transferring the second MIS structure to the second MIS memory structure is performed after the first MIS structure is transferred to the first MIS memory structure.

20 . The method of claim 16 , wherein the first metal electrode layer and the second metal electrode layer are vertically stacked over the semiconductor layer.