Memory device and manufacturing method thereof
A method of forming a memory device including providing a base wafer including a semiconductor material layer, and forming first and second spacers in the semiconductor material layer. The first spacers extend from a first surface of the semiconductor material layer to a second surface of the semiconductor material layer. The second spacers cross the first spacers and extend from the first surface of the semiconductor material layer to a position inside the semiconductor material layer. A plurality of semiconductor material strips are formed each between bottoms of the second spacers and the second surface of the semiconductor material layer and sandwiched between two neighboring first spacers. The method further includes performing a silicidation process at the second surface of the semiconductor material layer to convert at least portion of each of the semiconductor material strips into a silicide layer.
1 . A method of forming a memory device comprising:
providing a base wafer, the base wafer including a semiconductor material layer;
forming a plurality of first spacers in the semiconductor material layer, the plurality of first spacers extending from a first surface of the semiconductor material layer to a second surface of the semiconductor material layer;
forming a plurality of second spacers in the semiconductor material layer, the plurality of second spacers crossing the plurality of first spacers and extending from the first surface of the semiconductor material layer to a position inside the semiconductor material layer, providing a plurality of semiconductor material strips each being between bottoms of the second spacers and the second surface of the semiconductor material layer; and
performing a silicidation process at the second surface of the semiconductor material layer to convert at least portion of each of the semiconductor material strips into a silicide layer, wherein the silicide layer extends from the second surface of the semiconductor material layer into the semiconductor material layer and is sandwiched between two neighboring ones of the plurality of first spacers at the second surface.
2 . A memory device comprising:
a semiconductor material layer;
a plurality of first spacers in the semiconductor material layer, the plurality of first spacers extending from a first surface of the semiconductor material layer to a second surface of the semiconductor material layer;
a plurality of second spacers in the semiconductor material layer, the plurality of second spacers crossing the plurality of first spacers and extending from the first surface of the semiconductor material layer to a position inside the semiconductor material layer; and
a plurality of silicide layers extending from the second surface of the semiconductor material layer into the semiconductor material layer, each of the plurality of silicide layers having a strip shape and being sandwiched between two neighboring ones of the plurality of first spacers at the second surface.
3 . The memory device of claim 2 , further comprising:
a plurality of semiconductor material strips each being sandwiched between two neighboring ones of the first spacers along a direction perpendicular to an extending direction of the plurality of first spacers between the first and second surfaces, and being between the second spacers and a corresponding one of the plurality of silicide layers along the extending direction of the plurality of first spacers.
4 . The memory device of claim 2 , further comprising:
a plurality of active area (AA) pillars including a portion of the semiconductor material layer sandwiched between two neighboring ones of the plurality of first spacers and further between two neighboring ones of the plurality of second spacers, wherein the plurality of silicide layers are aligned with the plurality of active area (AA) pillars.
5 . The memory device of claim 2 , further comprising:
a plurality of gate structures each being buried in a corresponding one of the plurality of second spacers and being on sidewalls of a corresponding column of a plurality of active area (AA) pillars, each of the plurality of AA pillars including a portion of the semiconductor material layer sandwiched between two neighboring ones of the plurality of first spacers and between two neighboring ones of the plurality of second spacers;
wherein each of the plurality of gate structures includes:
a gate dielectric layer on the sidewalls of the corresponding column of the plurality of AA pillars; and
a gate electrode layer on the gate dielectric layer.
6 . The memory device of claim 2 , further comprising:
an insulation layer over the second surface of the semiconductor material layer; and
a plurality of lead-out structures in the insulation layer, each of the plurality of lead-out structures being in contact with a corresponding one of the plurality of silicide layers.
7 . The memory device of claim 6 , wherein each of the plurality of lead-out structures has a strip shape.
8 . A memory system comprising:
a memory device including:
a semiconductor material layer;
a plurality of first spacers in the semiconductor material layer, the plurality of first spacers extending from a first surface of the semiconductor material layer to a second surface of the semiconductor material layer;
a plurality of second spacers crossing the plurality of first spacers and extending from the first surface of the semiconductor material layer to a position inside the semiconductor material layer; and
a plurality of silicide layers extending from the second surface of the semiconductor material layer into the semiconductor material layer, the plurality of silicide layers each being sandwiched between two neighboring ones of the plurality of first spacers at the second surface; and
a memory controller coupled to the memory device and configured to control operation of the memory device.
9 . The system of claim 8 , further comprising:
a plurality of semiconductor material strips each being sandwiched between two neighboring ones of the first spacers along a direction perpendicular to an extending direction of the plurality of first spacers between the first and second surfaces, and being between the second spacers and a corresponding one of the plurality of silicide layers along the extending direction of the plurality of first spacers.
10 . The system of claim 8 , further comprising:
a plurality of active area (AA) pillars including a portion of the semiconductor material layer sandwiched between two neighboring ones of the plurality of first spacers and further between two neighboring ones of the plurality of second spacers, wherein the plurality of silicide layers are aligned with the plurality of active area (AA) pillars.
11 . The system of claim 8 , wherein:
each of the plurality of silicide layers is converted from a portion of a corresponding semiconductor material strip that is away from bottoms of the second spacers.
12 . The system of claim 8 , wherein:
the plurality of first spacers are arranged in a row along a first direction and extend along a second direction; and
the plurality of second spacers are arranged in a row along the second direction and extend along the first direction.
13 . The system of claim 8 , further comprising:
a plurality of gate structures each being buried in a corresponding one of the plurality of second spacers and being on sidewalls of a corresponding column of a plurality of active area (AA) pillars, each of the plurality of AA pillars including a portion of the semiconductor material layer sandwiched between two neighboring ones of the plurality of first spacers and between two neighboring ones of the plurality of second spacers;
wherein each of the plurality of gate structures includes:
a gate dielectric layer on the sidewalls of the corresponding column of the plurality of AA pillars; and
a gate electrode layer on the gate dielectric layer.
14 . The system of claim 13 , wherein:
an insulation layer is disposed over a first surface of the semiconductor material layer;
a plurality of first conductive structures are formed in the insulation layer, each of the plurality of first conductive structures having a pillar shape and contacting a corresponding one of the plurality of active area (AA) pillars.
15 . The system of claim 14 , wherein:
a plurality of second conductive structures are formed in the insulation layer, each of the plurality of second conductive structures having a strip shape and contacting a corresponding column of the plurality of first conductive structures.
16 . The system of claim 8 , further comprising:
an insulation layer over the second surface of the semiconductor material layer; and
a plurality of lead-out structures in the insulation layer, each of the plurality of lead-out structures being in contact with a corresponding one of the plurality of silicide layers.
17 . The system of claim 16 , wherein each of the plurality of lead-out structures has a strip shape.
18 . The memory device of claim 2 , wherein:
each of the plurality of silicide layers is converted from a portion of a corresponding semiconductor material strip that is away from bottoms of the second spacers.
19 . The memory device of claim 2 , wherein:
the plurality of first spacers are arranged in a row along a first direction and extend along a second direction; and
the plurality of second spacers are arranged in a row along the second direction and extend along the first direction.
20 . The memory device of claim 5 , wherein:
an insulation layer is disposed over a first surface of the semiconductor material layer;
a plurality of first conductive structures are formed in the insulation layer, each of the plurality of first conductive structures having a pillar shape and contacting a corresponding one of the plurality of active area (AA) pillars; and
a plurality of second conductive structures are formed in the insulation layer, each of the plurality of second conductive structures having a strip shape and contacting a corresponding column of the plurality of first conductive structures.