Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a stacked body with first conductive layers and first insulating layers alternately stacked. The stacked body includes a staircase portion in which the first conductive layers are in a staircase shape. A columnar portion extends in a stacking direction through the stacked body at the staircase portion. The columnar portion includes a semiconductor layer, a second insulating layer covering a side wall of the semiconductor layer, and a third insulating layer that covers the second insulating layer. The third insulating layer includes a material different from the second insulating layer and includes flanged portions that protrude from a sidewall thereof toward the first conductive layers at corresponding height positions.
1 . A semiconductor memory device, comprising:
a stacked body with a plurality of first conductive layers and a plurality of first insulating layers alternately stacked, the stacked body having a connection region in which a plurality of contacts are connected to the plurality of first conductive layers;
a pillar that extends in a stacking direction through the stacked body in a region away from the connection region in a first direction intersecting the stacking direction, memory cells being at intersections of the pillar with at least some of the plurality of first conductive layers; and
a columnar portion that extends in the stacking direction through the stacked body at the connection region, wherein
the columnar portion includes:
a first semiconductor layer extending in the stacking direction,
a second insulating layer covering a side wall of the first semiconductor layer, and
a third insulating layer covering a side wall of the second insulating layer, the third insulating layer comprising a material different from that of the second insulating layer and including a plurality of flanged portions on a sidewall thereof, the flanged portions protruding toward a side of the plurality of first conductive layers at height positions corresponding to the plurality of first conductive layers.
2 . The semiconductor memory device according to claim 1 , wherein
at least one flanged portion of the plurality of flanged portions contains a void inside.
3 . The semiconductor memory device according to claim 1 , wherein
the third insulating layer has an insulating layer part that covers the side wall of the second insulating layer and extends along the stacking direction, and
when viewed from the stacking direction, a center position of each of the plurality of flanged portions at the height positions corresponding to the plurality of first conductive layers is substantially coincident with a center position of the insulating layer part at respective height positions of each of the plurality of flanged portions.
4 . The semiconductor memory device according to claim 1 , wherein
the third insulating layer includes an insulating layer part that covers the side wall of the second insulating layer and extends along the stacking direction, and
when viewed from the stacking direction, a cross-sectional shape of each of the plurality of flanged portions at the height positions corresponding to the plurality of first conductive layers is substantially similar to a cross-sectional shape of the insulating layer part at respective height positions of each of the plurality of flanged portions.
5 . The semiconductor memory device according to claim 1 , wherein the pillar includes:
a second semiconductor layer extending in the stacking direction,
a fourth insulating layer comprising the same material as the second insulating layer and covering a side wall of the second semiconductor layer, and
a fifth insulating layer comprising the same material as the third insulating layer and covering a side wall of the fourth insulating layer.
6 . The semiconductor memory device according to claim 5 , wherein
the second and fourth insulating layers are nitride layers, and
the third and fifth insulating layers are oxide layers.
7 . A semiconductor memory device, comprising:
a stacked body with a plurality of first conductive layers and a plurality of first insulating layers alternately stacked, the stacked body having a staircase portion in which the plurality of first conductive layers are in a staircase shape;
an upper insulating layer covering the staircase portion;
a pillar that extends in a stacking direction through the stacked body in a region away from the staircase portion in a first direction intersecting the stacking direction, memory cells being at intersections of the pillar with at least some of the plurality of first conductive layers; and
a columnar portion that extends in the stacking direction through the upper insulating layer and the stacked body at the staircase portion, wherein
the columnar portion includes:
a first semiconductor layer extending in the stacking direction through the upper insulating layer and the stacked body,
a second insulating layer covering a side wall of the first semiconductor layer, and
a third insulating layer covering a side wall of the second insulating layer, the third insulating layer comprising a material different from that of the second insulating layer, and
an outer edge of the third insulating layer at a first height position corresponding to a position along the stacking direction of an uppermost one of the plurality of first conductive layers in the staircase portion of the stacked body is at a position that is outside a region that is surrounded by a virtual line formed when the outer edge of the third insulating layer at a second height position corresponding to a position along the stacking direction of a lower surface of the upper insulating layer that is above the uppermost one of the plurality of first conductive layers is projected downward to the first height position from the second height position.
8 . The semiconductor memory device according to claim 7 , wherein
there is no step in the second insulating layer at a boundary between the upper insulating layer and the stacked body, and
the second insulating layer extends in the stacking direction in the staircase portion of the stacked body and in the upper insulating layer.
9 . The semiconductor memory device according to claim 7 , wherein
the third insulating layer covers the side wall of the second insulating layer and extends in the stacking direction, and
when viewed from the stacking direction, the third insulating layer at third height positions of each of the plurality of first conductive layers widens substantially concentrically from an outer edge of the second insulating layer at the third height positions.
10 . The semiconductor memory device according to claim 7 , wherein, when viewed from the stacking direction, the uppermost one of the plurality of first conductive layers surrounds the columnar portion at a substantially equal distance from a center of the columnar portion.
11 . The semiconductor memory device according to claim 7 , wherein the third insulating layer contains a void at a height position of at least one first conductive layer in the plurality of first conductive layers.
12 . The semiconductor memory device according to claim 7 , wherein the pillar includes:
a second semiconductor layer extending in the stacking direction,
a fourth insulating layer comprising the same material as the second insulating layer and covering a side wall of the second semiconductor layer, and
a fifth insulating layer comprising the same material as the third insulating layer and covering a side wall of the fourth insulating layer.
13 . The semiconductor memory device according to claim 12 , wherein
the second and fourth insulating layers are nitride layers, and
the third and fifth insulating layers are oxide layers.
14 . A semiconductor memory device, comprising:
a stacked body with a plurality of first conductive layers and a plurality of first insulating layers alternately stacked, the stacked body having a staircase portion in which the plurality of first conductive layers are in a staircase shape;
a second conductive layer that is below the stacked body;
a pillar that extends in a stacking direction through the stacked body in a region away from the staircase portion in a first direction intersecting the stacking direction, memory cells being at intersections of the pillar with at least some of the plurality of first conductive layers; and
a columnar portion that extends in the stacking direction through the stacked body at the staircase portion and reaches the second conductive layer, wherein
the columnar portion includes:
a first semiconductor layer extending in the stacking direction,
a second insulating layer covering a side wall of the first semiconductor layer, and
a third insulating layer covering a side wall of the second insulating layer, the third insulating layer comprising a material different from that of the second insulating layer, and
an outer edge of the third insulating layer at a first height position corresponding to a position along the stacking direction of a lowermost one of the plurality of first conductive layers in the staircase portion of the stacked body is at a position that is outside a region that is surrounded by a virtual line formed when the outer edge of the third insulating layer at a second height position corresponding to a position along the stacking direction of an upper surface of the second conductive layer is projected upward to the first height position from the second height position.
15 . The semiconductor memory device according to claim 14 , wherein
the second insulating layer extends in the stacking direction and reaches to a position below the second height position without a step change at a boundary between the stacked body and the second conductive layer.
16 . The semiconductor memory device according to claim 14 , wherein, when viewed from the stacking direction, the third insulating layer at third height positions of each of the plurality of first conductive layers widens substantially concentrically from an outer edge of the second insulating layer at the third height positions.
17 . The semiconductor memory device according to claim 14 , wherein, when viewed from the stacking direction, the lowermost one of the plurality of first conductive layers surrounds the columnar portion at a substantially equal distance from a center of the columnar portion.
18 . The semiconductor memory device according to claim 14 , wherein the third insulating layer contains a void at a height position of at least one first conductive layer in the plurality of first conductive layers.
19 . The semiconductor memory device according to claim 14 , wherein the pillar includes:
a second semiconductor layer extending in the stacking direction,
a fourth insulating layer comprising the same material as the second insulating layer and covering a side wall of the second semiconductor layer, and
a fifth insulating layer comprising the same material as the third insulating layer and covering a side wall of the fourth insulating layer.
20 . The semiconductor memory device according to claim 19 , wherein
the second and fourth insulating layers are nitride layers, and
the third and fifth insulating layers are oxide layers.