Method for fabricating semiconductor memory device with source coupling structure
A method of manufacturing a semiconductor memory device includes forming a preliminary source structure including a source sacrificial layer, forming a preliminary stacked structure including insulating layers and first sacrificial layers over the preliminary source structure, forming a slit passing through the preliminary stacked structure, removing the first sacrificial layers through the slit to define first recess regions between the insulating layers, forming a second sacrificial layer in each of the first recess regions, removing the source sacrificial layer through the slit to define a second recess region, and forming a source channel coupling layer in the second recess region.
1 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a preliminary source structure including a source sacrificial layer;
forming a preliminary stacked structure including insulating layers and first sacrificial layers alternately stacked with each other over the preliminary source structure;
forming a slit passing through the preliminary stacked structure;
removing the first sacrificial layers through the slit to define first recess regions between the insulating layers;
forming a second sacrificial layer in each of the first recess regions;
removing the source sacrificial layer through the slit to define a second recess region after forming the second sacrificial layer; and
forming a source channel coupling layer in the second recess region.
2 . The method of claim 1 , further comprising forming a liner layer along the first recess regions after the first recess regions are formed.
3 . The method of claim 2 , wherein the liner layer includes a metal-doped oxide.
4 . The method of claim 1 , wherein the first sacrificial layers include a nitride, and wherein the second sacrificial layer includes an oxide.
5 . The method of claim 1 , further comprising replacing the second sacrificial layer with a conductive layer.
6 . The method of claim 5 , wherein replacing the second sacrificial layer by the conductive layer is performed after forming the source channel coupling layer.
7 . The method of claim 1 , wherein removing the source sacrificial layer includes a wet etching process.
8 . The method of claim 1 , wherein the preliminary source structure includes a source protective layer disposed on each of an upper surface and a lower surface of the source sacrificial layer.
9 . The method of claim 8 , further comprising removing the source protective layer after removing the source sacrificial layer.
10 . The method of claim 1 , further comprising:
extending the slit into the preliminary source structure after forming the second sacrificial layer; and
forming an oxide layer on a surface of the preliminary source structure that is exposed through the slit.
11 . The method of claim 1 , wherein the preliminary source structure further includes a first source layer under the source sacrificial layer and a second source layer over the source sacrificial layer.
12 . The method of claim 11 , further comprising:
forming a hole that passes through the second source layer and the source sacrificial layer and extends into the first source layer;
forming a memory layer in the hole; and
forming a channel structure in a central region of the memory layer.
13 . The method of claim 12 , further comprising removing a part of the memory layer through the second recess region such that the memory layer is divided into a first memory layer over the second recess region and a second memory layer under the second recess region.
14 . The method of claim 13 , wherein the source channel coupling layer passes between the first and second memory layers and is directly coupled to the channel structure.