Semiconductor devices and data storage systems including the same
A semiconductor device includes a lower structure; a pattern structure including first to third pattern layers sequentially stacked on the lower structure; gate electrodes stacked on the pattern structure and spaced apart from each other in a first direction that is perpendicular to an upper surface of the pattern structure, and a channel structure passing through the gate electrodes. The channel structure includes a channel layer and a metal-semiconductor compound layer. The metal-semiconductor compound layer contacts the channel layer and the second pattern layer. The channel structure passes through the second and third pattern layers and extends into the first pattern layer. The second pattern layer has a first metal layer contacting the metal-semiconductor compound layer. At least a portion of the metal-semiconductor compound layer overlaps the lower gate electrode in a second direction perpendicular to the first direction.
1 . A semiconductor device comprising:
a lower structure;
a pattern structure including a first pattern layer, a second pattern layer, and a third pattern layer,
the first pattern layer, the second pattern layer, and the third pattern layer being sequentially stacked on the lower structure, and
the first pattern layer and the third pattern layer having a semiconductor material;
the second pattern layer having a first metal layer;
a plurality of gate electrodes stacked on the pattern structure and spaced apart from each other in a first direction, the first direction being perpendicular to an upper surface of the pattern structure, and the plurality of gate electrodes including a lower gate electrode in a lower portion within the plurality of gate electrodes; and
a channel structure passing through the plurality of gate electrodes, the channel structure including a semiconductor channel layer and a metal-semiconductor compound layer, at least a portion of the semiconductor channel layer being in contact with a bottom portion of the metal-semiconductor compound layer,
the metal-semiconductor compound layer being in contact with the semiconductor channel layer and in contact with the first metal layer of the second pattern layer,
the channel structure passing through at least the second pattern layer and the third pattern layer and the channel structure extending into the first pattern layer,
the metal-semiconductor compound layer contacting the first metal layer of the second pattern layer, and
at least a portion of the metal-semiconductor compound layer overlapping the lower gate electrode in a second direction, the second direction being perpendicular to the first direction.
2 . The semiconductor device of claim 1 , wherein
a thickness of the metal-semiconductor compound layer is equal to a thickness of the semiconductor channel layer, and
a side surface of the semiconductor channel layer is coplanar with a side surface of the metal-semiconductor compound layer.
3 . The semiconductor device of claim 1 , wherein
the metal-semiconductor compound layer comprises a same metal element as the second pattern layer, and
the metal-semiconductor compound layer comprises a same semiconductor element as the semiconductor channel layer.
4 . The semiconductor device of claim 1 , wherein
the first pattern layer and the third pattern layer comprise polycrystalline silicon.
5 . The semiconductor device of claim 1 , wherein
the lower gate electrode is one of a plurality of lower gate electrodes included in the lower portion of the plurality of gate electrodes, and
the metal-semiconductor compound layer horizontally overlaps at least two lower gate electrodes among the plurality of lower gate electrodes.
6 . The semiconductor device of claim 1 , wherein a first portion of the semiconductor channel layer is below the metal-semiconductor compound layer, and a second portion of the semiconductor channel layer is above the metal-semiconductor compound layer.
7 . The semiconductor device of claim 1 , wherein
the channel structure further comprises an information storage structure,
the information storage structure covers at least a portion of an outer side surface of the semiconductor channel layer and at least a portion of an outer side surface of the metal-semiconductor compound layer, and the second pattern layer passes through the information storage structure and contacts the metal-semiconductor compound layer.
8 . The semiconductor device of claim 7 , wherein
the lower structure comprises a base substrate and a peripheral circuit disposed on the base substrate, and
a thickness of the second pattern layer in a region between the first pattern layer and the third pattern layer is thinner than a thickness of the second pattern layer in a region passing through the information storage structure.
9 . The semiconductor device of claim 1 , wherein the channel structure further comprises:
a channel buried insulating layer; and
a conductive pad on the channel buried insulating layer,
wherein the channel buried insulating layer covers an inner side surface of the semiconductor channel layer.
10 . The semiconductor device of claim 9 , wherein the plurality of gate electrodes includes an upper gate electrode in an upper portion within the plurality of gate electrodes,
the channel structure further comprises an upper metal-semiconductor compound layer extending from an outer side surface of the conductive pad,
at least a portion of the upper metal-semiconductor compound layer horizontally overlaps the upper gate electrode in the second direction,
the conductive pad comprises a second metal layer, and
a lower surface of the second metal layer is located on a level higher than an upper surface of the upper gate electrode.
11 . The semiconductor device of claim 9 , wherein
the plurality of gate electrodes comprise an upper gate electrode in an upper portion within the gate electrodes,
the conductive pad comprises a second metal layer, and
at least a portion of the conductive pad horizontally overlaps the upper gate electrode in the second direction.
12 . The semiconductor device of claim 11 , wherein the semiconductor channel layer extends onto an outer side surface of the conductive pad, and
the channel structure further includes an upper metal-semiconductor compound layer disposed on the semiconductor channel layer and the outer side surface of the conductive pad.
13 . A semiconductor device comprising:
a first horizontal conductive layer including a metal layer;
a second horizontal conductive layer on the first horizontal conductive layer and including a semiconductor material;
a plurality of gate electrodes stacked on the second horizontal conductive layer and spaced apart from each other in a first direction, the first direction being perpendicular to an upper surface of the first horizontal conductive layer; and
a channel structure passing through the plurality of gate electrodes and the second horizontal conductive layer, the channel structure including a semiconductor channel layer and a lower metal-semiconductor compound layer, at least a portion of the semiconductor channel layer being in contact with a bottom portion of the lower metal-semiconductor compound layer,
the lower metal-semiconductor compound layer being in contact with the semiconductor channel layer and in contact with the metal layer of the first horizontal conductive layer,
the first horizontal conductive layer being in contact with a lower surface of the second horizontal conductive layer,
the first horizontal conductive layer covering at least a portion of a side surface of the second horizontal conductive layer,
the lower metal-semiconductor compound layer extending in a direction facing the plurality of gate electrodes from a region contacting the first horizontal conductive layer, and
a level of an upper surface of the lower metal-semiconductor compound layer being higher than an upper surface of the second horizontal conductive layer.
14 . The semiconductor device of claim 13 , wherein the channel structure further comprises:
a channel buried insulating layer;
a conductive pad covering the channel buried insulating layer; and
an upper metal-semiconductor compound layer contacting the semiconductor channel layer and the conductive pad.
15 . The semiconductor device of claim 13 , wherein the channel structure further comprises an information storage structure,
the information storage structure covers at least a portion of an outer side surface of the semiconductor channel layer and at least a portion of an outer side surface of the lower metal-semiconductor compound layer,
the information storage structure comprises a tunneling layer, a blocking layer, and an information storage layer between the tunneling layer and the blocking layer, and
the first horizontal conductive layer passes through the information storage structure and contacts the lower metal-semiconductor compound layer.
16 . The semiconductor device of claim 14 , wherein
the upper metal-semiconductor compound layer covers an outer side surface of the conductive pad, and
the semiconductor channel layer covers an outer side surface of the upper metal-semiconductor compound layer.
17 . The semiconductor device of claim 14 , wherein the plurality of gate electrodes comprise a lower gate electrode, a plurality of intermediate gate electrodes on the lower gate electrode, and an upper gate electrode on the plurality of intermediate gate electrodes,
a portion of the upper metal-semiconductor compound layer overlaps the upper gate electrode in a second direction,
the second direction is perpendicular to the first direction, and
a portion of the lower metal-semiconductor compound layer overlaps the lower gate electrode in the second direction.
18 . The semiconductor device of claim 17 , wherein a portion of the conductive pad overlaps the upper gate electrode in the second direction.
19 . A data storage system comprising:
a semiconductor storage device including a lower structure including circuit elements, a pattern structure including a plurality of pattern layers sequentially stacked on the lower structure, a plurality of gate electrodes stacked on the pattern structure and spaced apart from each other in a first direction, a channel structure passing through the plurality of gate electrodes, and an input/output pad electrically connected to the circuit elements,
the plurality of pattern layers including a first pattern layer, a second pattern layer, and a third pattern layer, the first pattern layer, the second pattern layer, and the third pattern layer being sequentially stacked on the lower structure,
the first direction being perpendicular to an upper surface of the pattern structure,
the plurality of gate electrodes including a lower gate electrode in a lower portion within the gate electrodes,
the channel structure including a semiconductor channel layer and a metal-semiconductor compound layer, at least a portion of the semiconductor channel layer being in contact with a bottom portion of the metal-semiconductor compound layer,
the metal-semiconductor compound layer being in contact with the semiconductor channel layer and in contact with the second pattern layer,
the channel structure passing through at least the second pattern layer and the third pattern layer and the channel structure extending into the first pattern layer,
the first pattern layer and the third pattern layer comprise a semiconductor material,
the second pattern layer having a first metal layer contacting the metal-semiconductor compound layer, and
at least a portion of the metal-semiconductor compound layer overlapping the lower gate electrode in a second direction, the second direction being perpendicular to the first direction; and
a controller electrically connected to the semiconductor storage device through the input/output pad and configured to control the semiconductor storage device.
20 . The data storage system of claim 19 , wherein
the plurality of gate electrodes further include an upper gate electrode in an upper portion within the plurality of gate electrodes,
the channel structure further comprises a channel buried insulating layer and a conductive pad,
the channel buried insulating layer covers an inner side surface of the semiconductor channel layer, the conductive pad is on the channel buried insulating layer,
the conductive pad comprises a second metal layer, and
a lower surface of the conductive pad is located at a level lower than an upper surface of the upper gate electrode.