Three-dimensional memory device with through-stack contact via with conductive fins

1 . A memory device, comprising:

a first alternating stack of first insulating layers and first electrically conductive layers, wherein the first alternating stack comprises first stepped surfaces in a contact region;

a first dielectric material portion overlying the first stepped surfaces of the first alternating stack;

a memory opening vertically extending at least through each layer within the first alternating stack;

a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel; and

a first contact via structure vertically extending at least from a bottommost surface of the first alternating stack, through the first dielectric material portion, and to a horizontal plane located at or above a top surface of the memory opening fill structure, wherein the first contact via structure comprises a conductive pillar portion and a conductive fin portion that laterally protrudes from the conductive pillar portion and the conductive fin portion having a first annular bottom surface segment contacting an annular top surface segment of one of the first electrically conductive layers.

2 . The memory device of claim 1 , further comprising a vertical stack of annular insulating plates laterally surrounding and contacting the conductive pillar portion and underlying the conductive fin portion.

3 . The memory device of claim 2 , wherein a topmost annular insulating plate within the vertical stack of annular insulating plates is in contact with a second annular bottom surface segment of the conductive fin portion.

4 . The memory device of claim 2 , further comprising backside blocking dielectric layers, wherein each of the backside blocking dielectric layers embeds a respective one of the first electrically conductive layers and is interposed between the respective one of the first electrically conductive layers and a respective one of the first insulating layers.

5 . The memory device of claim 4 , wherein each annular insulating plate within the vertical stack of annular insulating plates contacts a sidewall of a respective one of the backside blocking dielectric layers.

6 . The memory device of claim 2 , wherein each annular insulating plate within the vertical stack of annular insulating plates has a lateral width which laterally offsets a respective one of the electrically conductive layers located at a same vertical level from the conductive pillar portion by a uniform lateral offset distance.

7 . The memory device of claim 1 , wherein the conductive fin portion comprises an annular top surface in contact with an annular planar surface segment of the first dielectric material portion.

8 . The memory device of claim 7 , wherein the conductive pillar portion comprises:

a first cylindrical surface vertically extending through the first dielectric material portion and having a bottom periphery that is adjoined to an inner periphery of the annular top surface of the conductive fin portion; and

a second cylindrical surface vertically extending through a subset of layers within the first alternating stack and having a top periphery that is adjoined to a bottom surface of the conductive fin portion.

9 . The memory device of claim 1 , further comprising a composite dielectric layer interposed between the first stepped surfaces and the first dielectric material portion and including a blocking dielectric liner and a dielectric fill material layer embedded within the blocking dielectric liner, wherein the blocking dielectric liner contacts each top surface of the dielectric fill material layer and each bottom surface of the dielectric fill material layer.

10 . The memory device of claim 9 , wherein the conductive fin portion contacts a sidewall of the dielectric fill material layer.

11 . The memory device of claim 9 , further comprising backside blocking dielectric layers interposed between each neighboring pair of a first electrically conductive layer and a first insulating layer within the first alternating stack and having a same material composition and a same thickness as the blocking dielectric liner.

12 . The memory device of claim 9 , wherein:

the composite dielectric layer comprises horizontally-extending portions and vertically-extending potions that are interconnected over the first stepped surfaces; and

a vertical thickness of the horizontally-extending portions and a lateral thickness of the vertically-extending portions are the same, and are greater than an inter-layer gap between vertically neighboring pairs of the first insulating layers within the first alternating stack.

13 . The memory device of claim 1 , further comprising:

a second alternating stack of second insulating layers and second electrically conductive layers located the first alternating stack, wherein the second alternating stack comprises second stepped surfaces in the contact region, and wherein the memory opening fill structure vertically extends through the second alternating stack; and

a second dielectric material portion overlying the second stepped surfaces of the second alternating stack.

14 . The memory device of claim 13 , further comprising a second contact via structure vertically extending at least from the bottommost surface of the first alternating stack to the horizontal plane located at or above the top surface of the memory opening fill structure and comprising an additional conductive pillar portion and an additional conductive fin portion that laterally protrudes from the additional conductive pillar portion and having an additional annular bottom surface segment contacting an annular top surface segment of one of the second electrically conductive layers.