Semiconductor memory device
A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes a gate stack, a pass gate overlapping a contact region of the gate stack and opening a cell array region of the gate stack, a doped semiconductor layer spaced apart from the pass gate and overlapping the cell array region of the gate stack, and an active pillar passing through the pass gate.
1 . A semiconductor memory device comprising:
a gate stack including a plurality of conductive patterns spaced apart from each other in a first direction and stacked in the first direction, the gate stack including a contact region and a cell array region extending from the contact region in a second direction crossing the first direction;
a pass gate overlapping the contact region of the gate stack and opening the cell array region of the gate stack;
a doped semiconductor layer spaced apart from the pass gate in the second direction and overlapping the cell array region of the gate stack; and
a plurality of active pillars passing through the pass gate.
2 . The semiconductor memory device of claim 1 , wherein a side of the pass gate includes a region overlapping a side of the doped semiconductor layer.
3 . The semiconductor memory device of claim 1 , further comprising:
a channel pillar including a first portion extending in the first direction and passing through the cell array region of the gate stack, and a second portion extending from the first portion and embedded in the doped semiconductor layer; and
a memory layer between the first portion of the channel pillar and the gate stack.
4 . The semiconductor memory device of claim 3 , wherein a side of the pass gate includes a region overlapping the second portion of the channel pillar.
5 . The semiconductor memory device of claim 1 , further comprising:
a peripheral circuit structure overlapping the pass gate with the gate stack interposed between the peripheral circuit structure and the pass gate.
6 . The semiconductor memory device of claim 1 , further comprising:
a plurality of gate contact plugs passing through the contact region of the gate stack and respectively contacting the plurality of active pillars,
wherein each gate contact plug of the plurality of gate contact plugs includes a contact surface contacting a corresponding conductive pattern among the plurality of conductive patterns.
7 . The semiconductor memory device of claim 6 , further comprising:
a plurality of insulating spacers interposed between adjacent gate contact plugs and conductive patterns among the plurality of gate contact plugs and the plurality of conductive patterns,
wherein the plurality of insulating spacers comprises:
a first insulating spacer adjacent to the contact surface of each gate contact plug of the plurality of gate contact plugs; and
a second insulating spacer spaced apart from the contact surface of each gate contact plug of the plurality of gate contact plugs and formed in an annular shape to surround a side of each gate contact plug of the plurality of gate contact plugs.
8 . The semiconductor memory device of claim 1 , further comprising:
a pass gate insulating layer disposed between each active pillar of the plurality of active pillars and the pass gate.
9 . The semiconductor memory device of claim 1 , wherein each active pillar of the plurality of active pillars comprises:
a first junction facing the gate stack;
a second junction facing a direction opposite to that of the first junction; and
a channel region between the first junction and the second junction.
10 . The semiconductor memory device of claim 1 , further comprising:
a semiconductor pattern disposed between the doped semiconductor layer and the pass gate, the semiconductor pattern overlapping the gate stack;
a partition wall structure disposed between the semiconductor pattern and the pass gate; and
a partition wall insulating layer surrounding a side of the partition wall structure.
11 . The semiconductor memory device of claim 10 , wherein the semiconductor pattern includes the same material as the pass gate, and
wherein the partition wall structure includes the same material as the plurality of active pillars.
12 . The semiconductor memory device of claim 1 , wherein a plurality of ends of the plurality of conductive patterns respectively overlap the plurality of active pillars and form a stepped structure in the contact region of the gate stack.
13 . A semiconductor memory device comprising:
a peripheral circuit structure including a first region and a second region;
a pass gate spaced apart from the peripheral circuit structure in a first direction and overlapping the first region of the peripheral circuit structure;
doped semiconductor layer spaced apart from the peripheral circuit structure in the first direction and spaced apart from the pass gate in a second direction crossing the first direction;
a gate stack including a contact region between the peripheral circuit structure and the pass gate and a cell array region extending from the contact region to a region between the peripheral circuit structure and the doped semiconductor layer;
an active pillar passing through the pass gate;
a pass gate insulating layer between the pass gate and the active pillar;
a channel pillar contacting the doped semiconductor layer and passing through the cell array region of the gate stack;
a memory layer between the channel pillar and the gate stack; and
a gate contact plug connected to the active pillar and passing through the contact region of the gate stack.
14 . The semiconductor memory device of claim 13 , wherein the gate stack includes a plurality of conductive patterns spaced apart from each other in the first direction and stacked in the first direction, and
wherein the plurality of conductive patterns includes a first conductive pattern contacting the gate contact plug and a second conductive pattern insulated from the gate contact plug.
15 . The semiconductor memory device of claim 14 , further comprising:
a first insulating spacer interposed between the gate contact plug and the first conductive pattern and opening a contact surface between the gate contact plug and the first conductive pattern; and
a second insulating spacer interposed between the gate contact plug and the second conductive pattern and formed in an annular shape to surround a side of the gate contact plug.
16 . The semiconductor memory device of claim 13 , wherein the active pillar comprises:
a first junction contacting the gate contact plug;
a second junction facing a direction opposite to that of the first junction; and
a channel region between the first junction and the second junction.
17 . The semiconductor memory device of claim 13 , further comprising:
at least one upper insulating layer covering the pass gate and the doped semiconductor layer;
a global line and a common source line over the at least one upper insulating layer;
a first contact passing through the at least one upper insulating layer to connect the active pillar to the global line; and
a second contact passing through the at least one upper insulating layer to connect the doped semiconductor layer to the common source line.
18 . The semiconductor memory device of claim 13 , further comprising:
an interposition insulating layer including a first interposition portion between the gate stack and the pass gate and a second interposition portion between the gate stack and the doped semiconductor layer,
wherein the active pillar and the channel pillar extend to pass through the interposition insulating layer.
19 . The semiconductor memory device of claim 13 , further comprising:
a semiconductor pattern disposed between the doped semiconductor layer and the pass gate, the semiconductor pattern overlapping the gate stack;
a partition wall structure disposed between the semiconductor pattern and the pass gate; and
a partition wall insulating layer surrounding a side of the partition wall structure.