Semiconductor memory device and method for manufacturing semiconductor memory device
A semiconductor memory device includes a stacked body, a first metal layer, and a first columnar body. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers include a first gate electrode layer, and a second gate electrode layer having a length in a second direction intersecting a first direction that is shorter than that of the first gate electrode layer. The first metal layer is disposed at least on a first side with respect to a terrace portion of the first gate electrode layer. The first columnar body is disposed on the first side with respect to the terrace portion of the first gate electrode layer. The first columnar body includes a conductive portion extending in the first direction and penetrating the first metal layer to be connected to the terrace portion of the first gate electrode layer, and an insulator disposed at least between the first metal layer and the conductive portion.
1 . A semiconductor memory device comprising:
a stacked body including a plurality of gate electrode layers and a plurality of insulating layers, the plurality of gate electrode layers and the plurality of insulating layers being alternately stacked one by one in a first direction, the plurality of gate electrode layers including a first gate electrode layer and a second gate electrode layer, the second gate electrode layer being disposed on a first side in the first direction with respect to the first gate electrode layer, the second gate electrode layer having a length in a second direction intersecting the first direction that is shorter than that of the first gate electrode layer, the first gate electrode layer having a terrace portion that does not overlap with the second gate electrode layer in the first direction;
a first metal layer disposed at least on the first side with respect to the terrace portion of the first gate electrode layer; and
a first columnar body disposed on the first side with respect to the terrace portion of the first gate electrode layer, wherein
the first columnar body including a conductive portion and an insulating portion, the conductive portion extending in the first direction, the conductive portion penetrating the first metal layer and connected to the terrace portion of the first gate electrode layer, the insulating portion disposed at least between the first metal layer and the conductive portion, wherein
in a region overlapping with the terrace portion of the first gate electrode layer in the first direction, a thickness of the first metal layer in the first direction is greater than a thickness of the first gate electrode layer in the first direction.
2 . The semiconductor memory device according to claim 1 , wherein
at least a part of the first metal layer is aligned with the second gate electrode layer in the second direction.
3 . The semiconductor memory device according to claim 1 , further comprising:
a first insulating layer including a portion disposed between the first metal layer and the first gate electrode layer.
4 . The semiconductor memory device according to claim 1 , wherein
the first metal layer and the first gate electrode layer are made of a same material.
5 . The semiconductor memory device according to claim 1 , wherein
in a region overlapping with the terrace portion of the first gate electrode layer in the first direction, a thickness of the first metal layer in the first direction is 1.5 times or more than a thickness of the first gate electrode layer in the first direction.
6 . The semiconductor memory device according to claim 1 , wherein
the first metal layer is grounded.
7 . The semiconductor memory device according to claim 1 , wherein
the stacked body further includes a third gate electrode layer disposed on the first side with respect to the second gate electrode layer, the third gate electrode layer having a length in the second direction shorter than that of the second gate electrode layer,
the second gate electrode layer having a terrace portion that does not overlap with the third gate electrode layer in the first direction, and
the first metal layer includes a first portion, a second portion, and a step portion, the first portion disposed on the first side with respect to the terrace portion of the first gate electrode layer, the second portion disposed at a position different from the first portion in the first direction and disposed on the first side with respect to the terrace portion of the second gate electrode layer, and the step portion disposed between the first portion and the second portion and connecting the first portion and the second portion.
8 . The semiconductor memory device according to claim 7 , further comprising:
a second columnar body disposed on the first side with respect to the terrace portion of the second gate electrode layer, wherein
the first columnar body penetrates the first portion of the first metal layer and is connected to the terrace portion of the first gate electrode layer, and
the second columnar body penetrates the second portion of the first metal layer and is connected to the terrace portion of the second gate electrode layer.
9 . The semiconductor memory device according to claim 1 , further comprising:
a second metal layer; and
a third columnar body, wherein
the stacked body includes a first stacked body and a second stacked body, the first stacked body including at least two gate electrode layers in the plurality of gate electrode layers, and the second stacked body disposed on the first side with respect to the first stacked body and including at least two gate electrode layers in the plurality of gate electrode layers, wherein
the at least two gate electrode layers of the first stacked body include the first gate electrode layer and the second gate electrode layer, and
the at least two gate electrode layers of the second stacked body include a fourth gate electrode layer and a fifth gate electrode layer, the fifth gate electrode layer disposed on the first side with respect to the fourth gate electrode layer, and the fifth gate electrode layer having a length in the second direction shorter than that of the fourth gate electrode layer, wherein
the fourth gate electrode layer has a terrace portion that does not overlap with the fifth gate electrode layer in the first direction, and wherein
the second metal layer is disposed at least on the first side with respect to the terrace portion of the fourth gate electrode layer, and
the third columnar body (i) is disposed on the first side with respect to the terrace portion of the fourth gate electrode layer, (ii) extends in the first direction, (iii) penetrates the second metal layer, and (iv) is connected to the terrace portion of the fourth gate electrode layer.
10 . The semiconductor memory device according to claim 9 , wherein
the first metal layer and the second metal layer are separated from each other.
11 . The semiconductor memory device according to claim 1 , wherein
the insulating portion includes a first insulating portion and a second insulating portion, the first insulating portion disposed at a position separated from the first metal layer and the conductive portion and extending along the conductive portion, the second insulating portion disposed between the first metal layer and the conductive portion, and
a thickness of the second insulating portion in the second direction is greater than a thickness of the first insulating portion in the second direction.
12 . The semiconductor memory device according to claim 1 , wherein the semiconductor memory device includes a non-volatile semiconductor memory.
13 . The semiconductor memory device according to claim 1 , wherein the plurality of gate electrode layers include tungsten.
14 . The semiconductor memory device according to claim 1 , wherein the plurality of insulating layers include silicon oxide.
15 . The semiconductor memory device according to claim 1 , wherein the conductive portion includes tungsten.
16 . The semiconductor memory device according to claim 1 , wherein the insulating portion includes silicon oxide.