Semiconductor memory devices and methods of fabricating the same

1 . A semiconductor device, comprising:

a word line (WL) structure;

a ferroelectric layer over the WL structure;

a channel layer over the ferroelectric layer;

a source line (SL) structure over the channel layer, wherein the SL structure has sidewalls parallel to each other and extending from a top surface of the SL structure to a bottom surface of the SL structure;

a bit line (BL) structure over the channel layer, wherein the BL structure includes a portion laterally extending toward the SL structure;

a first dielectric layer laterally interposed between the SL structure and the BL structure; and

a second dielectric layer laterally interposed between the SL structure and the BL structure, wherein the first dielectric layer is disposed between the channel layer and the second dielectric layers,

wherein a top surface of the portion of the BL structure is coplanar with the top surface of the SL structure and a top surface of the second dielectric layer.

2 . The semiconductor device of claim 1 , wherein the portion of the BL structure partially extends along a top surface of the first dielectric layer.

3 . The semiconductor device of claim 2 , wherein the first dielectric layer and the second dielectric layer differ in composition.

4 . The semiconductor device of claim 2 , wherein the second dielectric layer has a width shorter than a width of the first dielectric layer.

5 . The semiconductor device of claim 2 , wherein the second dielectric layer partially extends along the top surface of the first dielectric layer.

6 . The semiconductor device of claim 1 , wherein the ferroelectric layer includes a multi-layer structure.

7 . The semiconductor device of claim 1 , wherein the first portion of the BL structure is physically separated from the channel layer.

8 . A semiconductor device, comprising:

a ferroelectric memory cell, including:

a word line (WL) structure;

a ferroelectric layer over the WL structure;

a channel layer over the ferroelectric layer;

a first dielectric layer over the channel layer;

an etch-stop layer over a portion of the first dielectric layer;

a second dielectric layer over the etch-stop layer, wherein the second dielectric layer has a composition different from the etch-stop layer;

a source line (SL) structure over the channel layer; and

a bit line (BL) structure over the channel layer and partially extending over the first dielectric layer toward the SL structure, wherein the second dielectric layer extends to contact a sidewall of each of the SL structure and the BL structure, and

wherein a top surface of the second dielectric layer, a top surface of the SL structure, and a top surface of the BL structure are coplanar with each other.

9 . The semiconductor device of claim 8 , wherein the second dielectric layer is disposed between the SL structure and the BL structure such that the SL structure is physically separated from the BL structure.

10 . The semiconductor device of claim 8 , wherein the first dielectric layer directly contacts a top surface of the channel layer.

11 . The semiconductor device of claim 8 , wherein the ferroelectric memory cell is a first ferroelectric memory cell, the semiconductor device further comprising a second ferroelectric memory cell adjacent to the first ferroelectric memory cell along a first direction, wherein the first ferroelectric memory cell has a first orientation and the second ferroelectric memory cell has the first orientation.

12 . The semiconductor device of claim 8 , further comprising a first via electrically connected to the SL structure and a second via electrically connected to the BL structure, the first via having a first cross-sectional area and the second via having a second cross-sectional area, wherein the first cross-sectional area is less than the second cross-sectional area.

13 . The semiconductor device of claim 8 , wherein at least one of the SL structure and the BL structure extends over a sidewall of the channel layer.

14 . The semiconductor device of claim 8 , wherein the channel layer has a width smaller than a width of the ferroelectric layer.

15 . The semiconductor device, comprising:

a word line (WL) structure on a semiconductor substrate;

a ferroelectric layer over the WL structure;

a channel layer over the ferroelectric layer;

a source line (SL) structure over the channel layer;

a bit line (BL) structure over the channel layer;

a first dielectric layer laterally interposed between the SL structure and the BL structure and disposed over the channel layer;

a second dielectric layer laterally interposed between the SL structure and the BL structure, wherein the second dielectric layer extends over a portion of the first dielectric layer;

a third dielectric layer disposed adjacent to the BL structure and over the ferroelectric layer; and

a fourth dielectric layer disposed adjacent to the WL structure and between the ferroelectric layer and the semiconductor substrate,

wherein a top surface of the third dielectric layer, a top surface of the SL structure and a top surface of the BL structure are coplanar with a top surface of the second dielectric layer.

16 . The semiconductor device of claim 15 , wherein one of the BL structure and the SL structure includes a portion extending toward the other.

17 . The semiconductor device of claim 15 , wherein a portion of the BL structure or a portion of the SL structure partially extends along a top surface of the first dielectric layer.

18 . The semiconductor device of claim 15 , further comprising an etch-stop layer over the first dielectric layer, wherein the etch-stop layer includes a portion that extends along a sidewall of the first dielectric layer.

19 . The semiconductor device of claim 15 , wherein the first dielectric layer and the second dielectric layer differ in composition.

20 . The semiconductor device of claim 15 , wherein the third dielectric layer directly contacts a sidewall of the SL structure.