Memory device and electronic device including the same

1 . A memory device comprising:

a plurality of gate electrodes spaced apart from each other in a first direction;

a memory layer comprising a plurality of memory regions that protrude in a second direction and extend in the second direction that is perpendicular to the first direction to face the plurality of gate electrodes, respectively;

a plurality of first insulating layers extended to spaces between the plurality of memory regions between the plurality of gate electrodes;

a channel layer between the memory layer and the plurality of gate electrodes, the channel layer having a shape including a plurality of first regions surrounding the plurality of memory regions and a second region that connects the plurality of first regions to each other in the first direction;

a gate insulating layer between the channel layer and the plurality of gate electrodes, wherein

the plurality of first regions comprise a first part and a third part facing each other with the plurality of memory regions between the first part and the third part, and a second part arranged between the first part and the third part and facing the plurality of gate electrodes,

both of the first part and the third part have a higher conductivity than the second part and

the first part and the third part of the channel layer serve as electrodes of a capacitor, and the second part serves as a channel of a transistor.

2 . The memory device of claim 1 , wherein an area in which each of the first part and the third part faces one of the plurality of memory regions is 0.003 μm 2 (square microns) or more and 0.025 μm 2 (square microns) or less.

3 . The memory device of claim 1 , further comprising:

a second insulating layer positioned between one of the plurality of memory regions and the second part.

4 . The memory device of claim 3 , wherein the second insulating layer comprises one or more of SiO, SiOC, or SiN, or defines an air gap.

5 . The memory device of claim 1 , wherein a protruding length of the plurality of memory regions is 10 nm or more to 100 nm or less.

6 . The memory device of claim 1 , wherein a length of the plurality of gate electrodes in the first direction is 20 nm or more to 100 nm or less.

7 . The memory device of claim 1 , wherein the memory layer comprises a ferroelectric material.

8 . The memory device of claim 7 , wherein the memory layer comprises at least one of an oxide of Hf, an oxide of Zr, AlScN, PZT, SBT, or BTO.

9 . The memory device of claim 1 , wherein the memory layer comprises a variable resistance material.

10 . The memory device of claim 9 , wherein the memory layer comprises an oxide of at least one of Rb, Ti, Ba, Zr, Ca, Hf, Sr, Sc, B, Mg, Al, K, Y, La, Si, Be, Nb, Ni, Ta, W, V, La, Gd, Cu, Mo, Cr, or Mn.

11 . The memory device of claim 1 , wherein the channel layer comprises at least one of

a Si, Ge, SiGe, and III-V group semiconductor,

an oxide semiconductor,

a nitride semiconductor,

an oxynitride semiconductor,

a two-dimensional (2D) material,

quantum dots, and

an organic semiconductor.

12 . The memory device of claim 1 , further comprising:

an insulating structure having a central axis parallel to the first direction, wherein

the memory layer surrounds the insulating structure,

the channel layer surrounds the memory layer, and

each of the plurality of gate electrodes surrounds the channel layer at different positions in the first direction.

13 . The memory device of claim 12 , wherein the memory device has a shape of a cylindrical or polygonal pillar.

14 . The memory device of claim 13 , further comprising:

a stepped wiring structure including wirings extending from each of the plurality of gate electrodes by different lengths in a third direction perpendicular to the first direction.

15 . A memory device comprising:

a semiconductor substrate; and

a plurality of memory cell strings extending in a first direction away from the semiconductor substrate on the semiconductor substrate, and arranged in two dimensions in a second direction and a third direction, which are perpendicular to the first direction, wherein

each of the plurality of memory cell strings comprises:

a plurality of gate electrodes spaced apart from each other in the first direction;

a memory layer comprising a plurality of memory regions that protrude in the second direction and extend in the second direction perpendicular to the first direction to face the plurality of gate electrodes, respectively;

a plurality of first insulating layers extending to spaces between the plurality of memory regions between the plurality of gate electrodes;

a channel layer between the memory layer and the plurality of gate electrodes, the channel layer having a shape including a plurality of first regions surrounding the plurality of memory regions and a second region that connects the plurality of first regions to each other along the first direction; and

a gate insulating layer between the channel layer and the plurality of gate electrodes, wherein

the plurality of first regions comprise a first part and a third part facing each other with the plurality of memory regions between the first part and the third part, and a second part arranged between the first part and the third part and facing the plurality of gate electrodes,

both of the first part and the third part have a higher conductivity than the second part and

the first part and the third part of the channel layer serve as electrodes of a capacitor, and the second part serves as a channel of a transistor.

16 . The memory device of claim 15 , wherein

each of the plurality of memory cell strings further comprises: a cylindrical insulating structure having a central axis parallel to the first direction, wherein

the memory layer surrounds the cylindrical insulating structure,

the channel layer surrounds the memory layer, and

each of the plurality of gate electrodes surrounds the channel layer at different positions in the first direction.

17 . An electronic device comprising:

a memory device including a memory cell array including a plurality of memory cells, and a voltage generator configured to generate a voltage to be applied to the memory cell array; and

a memory controller configured to control the memory device, wherein

the memory cell array comprises:

a plurality of gate electrodes spaced apart from each other in a first direction;

a memory layer comprising a plurality of memory regions that protrude in a second direction and that extend in the second direction that is perpendicular to the first direction to face the plurality of gate electrodes, respectively;

a plurality of first insulating layers extending to spaces between the plurality of memory regions between the plurality of gate electrodes;

a channel layer between the memory layer and the plurality of gate electrodes, the channel layer having a shape including a plurality of first regions surrounding the plurality of memory regions and a second region that connects the plurality of first regions to each other in the first direction; and

a gate insulating layer between the channel layer and the plurality of gate electrodes, wherein

the plurality of first regions comprise a first part and a third part facing each other with the plurality of memory regions between the first part and the third part, and a second part arranged between the first part and the third part and facing the plurality of gate electrodes,

both of the first part and the third part have a higher conductivity than the second part, and

the first part and the third part of the channel layer serve as electrodes of a capacitor, and the second part serves as a channel of a transistor.