Bit-line resistance reduction

1 . A method of forming an integrated chip structure, comprising:

forming a plurality of memory devices over a substrate;

forming a first dielectric stack over the plurality of memory devices;

patterning the first dielectric stack to form a common electrode opening extending laterally past tops of the plurality of memory devices;

forming a common electrode within the common electrode opening;

forming a first upper inter-level dielectric (ILD) layer over the common electrode;

patterning the first upper ILD layer to form a local interconnect opening that extends laterally past opposing edges of the common electrode;

forming a local interconnect within the local interconnect opening;

forming a plurality of interconnect vias within a second upper ILD layer that is over the first upper ILD layer; and

forming a bit-line over the plurality of interconnect vias, wherein the plurality of interconnect vias couple the local interconnect to the bit-line.

2 . A method of forming an integrated chip structure, comprising:

forming a plurality of memory devices over a substrate;

forming a first inter-level dielectric (ILD) layer to laterally surround the plurality of memory devices;

forming a peripheral lower interconnect within the first ILD layer;

forming a first dielectric stack over the plurality of memory devices and the first ILD layer;

forming a common electrode within the first dielectric stack, the common electrode laterally extending over the plurality of memory devices;

forming a second dielectric stack over the first dielectric stack and the common electrode;

forming a plurality of vias within the second dielectric stack and on the common electrode;

forming a second ILD layer over the second dielectric stack and the plurality of vias;

forming a peripheral via extending through a part of the second ILD layer, wherein the peripheral via is laterally outside of the plurality of memory devices and the common electrode, wherein the peripheral via has a bottommost surface that is at an equal height over the substrate as a bottommost surface of the common electrode, and wherein the peripheral lower interconnect contacts the bottommost surface of the peripheral via along an interface that is a non-zero distance vertically below a top of the common electrode, and wherein the peripheral lower interconnect laterally extends past an outermost sidewall of the peripheral via; and

forming an interconnect wire within the second ILD layer and on the plurality of vias.

3 . The method of claim 2 ,

wherein the first dielectric stack comprises a first plurality of dielectric layers stacked onto one another; and

wherein the second dielectric stack comprises a second plurality of dielectric layers stacked onto one another.

4 . The method of claim 2 , wherein a bottommost surface of the first dielectric stack is above a topmost surface of the plurality of memory devices.

5 . The method of claim 2 ,

wherein the second dielectric stack is formed over the first dielectric stack and along opposing outermost sidewalls of the first dielectric stack; and

wherein the second ILD layer is formed over the second dielectric stack and along opposing outermost sidewalls of the second dielectric stack.

6 . The method of claim 2 , further comprising:

forming a third ILD layer over the second ILD layer and the interconnect wire;

forming a plurality of upper vias within the third ILD layer and on the interconnect wire; and

forming an upper interconnect wire within the third ILD layer and on the plurality of upper vias.

7 . The method of claim 6 , wherein the upper interconnect wire laterally extends past opposing ends of the interconnect wire and the interconnect wire laterally extends past opposing ends of the common electrode.

8 . The method of claim 2 , wherein the first dielectric stack comprises a plurality of different layers of dielectric materials.

9 . The method of claim 2 , further comprising:

forming sidewall spacers along opposing sides of the plurality of memory devices, wherein the plurality of memory devices comprise a top electrode protruding outward to above a top of the sidewall spacers; and

forming a dielectric encapsulation layer along sides of the sidewall spacers, wherein the first ILD layer laterally surrounds the dielectric encapsulation layer and wherein the dielectric encapsulation layer has a topmost surface laterally extending between neighboring ones of the plurality of memory devices.

10 . The method of claim 9 , wherein opposing outermost sidewalls of the common electrode are separated by a first distance and opposing outermost sidewalls of the dielectric encapsulation layer are separated by a second distance that is larger than the first distance.

11 . The method of claim 2 , further comprising:

forming a dielectric encapsulation layer along sides of the plurality of memory devices, wherein the bottommost surface of the common electrode is a second non-zero distance vertically above a topmost surface of the dielectric encapsulation layer that laterally extends between neighboring ones of the plurality of memory devices.

12 . The method of claim 2 , wherein the first ILD layer comprises a topmost surface that laterally extends past the plurality of memory devices in opposing directions in a cross-sectional view, an entirety of the topmost surface being a second non-zero distance vertically above a topmost surface of the plurality of memory devices.

13 . A method of forming an integrated chip structure, comprising:

forming a plurality of memory devices over a substrate as viewed in a cross-sectional view;

forming a common electrode over the plurality of memory devices and continuously extending past outermost edges of the plurality of memory devices;

forming a local interconnect over the plurality of memory devices, wherein the common electrode is vertically between the local interconnect and the plurality of memory devices and is coupled to the local interconnect by way of a plurality of local interconnect vias;

forming a plurality of interconnect vias over the local interconnect;

forming a bit-line over the local interconnect, the bit-line extending in parallel to the local interconnect and past opposing ends of the local interconnect; and

wherein the local interconnect is coupled to the bit-line by the plurality of interconnect vias, the plurality of interconnect vias being disposed between a top of the local interconnect and a bottom of the bit-line.

14 . The method of claim 13 , wherein the plurality of interconnect vias are arranged within an array that laterally extends past two or more of the plurality of memory devices.

15 . The method of claim 13 , wherein the local interconnect laterally extends past opposing ends of the common electrode.

16 . The method of claim 13 , wherein the local interconnect has a greater width than the common electrode and the bit-line has a greater width than the local interconnect.

17 . The method of claim 13 , wherein the plurality of memory devices respectively comprise a magnetic tunnel junction (MTJ) disposed between a bottom electrode and a top electrode.

18 . The method of claim 13 , further comprising:

forming a plurality of interconnect islands onto upper surfaces of the plurality of interconnect vias;

forming a plurality of additional upper interconnect vias contacting upper surfaces of the plurality of interconnect islands; and

forming the bit-line onto upper surfaces of the plurality of additional upper interconnect vias.

19 . The method of claim 13 , wherein one or more additional memory devices are disposed laterally outside of the local interconnect, as viewed in the cross-sectional view.

20 . The method of claim 13 , further comprising:

forming a transistor device within a peripheral region of the substrate that surrounds an embedded memory region of the substrate comprising the plurality of memory devices, wherein the bit-line extends to within the peripheral region of the substrate and the local interconnect is confined within the embedded memory region of the substrate.