Thick redistribution layer features
Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a metal feature in a dielectric layer, a passivation structure over the dielectric layer and the metal feature, a contact pad over the passivation structure, and a plurality of contact vias extending through the passivation structure and in contact with the metal feature and the contact pad.
1 . A semiconductor structure, comprising:
a metal feature in a dielectric layer;
a passivation structure over the dielectric layer and the metal feature;
a contact pad over the passivation structure; and
a plurality of contact vias extending through the passivation structure and in contact with the metal feature and the contact pad,
wherein the metal feature comprises a first thickness,
wherein the contact pad comprises a second thickness greater than the first thickness,
wherein a ratio of the second thickness to the first thickness is between about 5 and about 10.
2 . The semiconductor structure of claim 1 , wherein the passivation structure includes:
a first passivation layer;
a metal-insulator-metal (MIM) capacitor disposed over and in contact with the first passivation layer; and
a second passivation layer disposed over and in contact with the MIM capacitor.
3 . The semiconductor structure of claim 2 ,
wherein the MIM capacitor includes a plurality of conductive plates interleaved by a plurality of insulation layers,
wherein the plurality of contact vias extend through at least one of the plurality of conductive plates.
4 . The semiconductor structure of claim 2 , wherein the first passivation layer and the second passivation layer comprise silicon nitride.
5 . The semiconductor structure of claim 2 , further comprising:
a protective layer disposed along sidewalls of the contact pad, wherein the protective layer comprises:
an inner layer disposed on the sidewalls of the contact pad, and
an outer layer disposed on the inner layer, wherein the outer layer is in contact with the inner layer and the sidewalls of the contact pad.
6 . The semiconductor structure of claim 5 , wherein a highest surface of the outer layer is higher than a highest surface of the inner layer.
7 . The semiconductor structure of claim 5 , wherein the inner layer and the outer layer comprise silicon nitride.
8 . A semiconductor structure, comprising:
a metal feature in a dielectric layer;
a passivation structure over the dielectric layer and the metal feature;
a contact pad over the passivation structure;
more than one contact via extending through the passivation structure and in contact with the metal feature and the contact pad;
a protective layer disposed along sidewalls of the contact pad;
a top passivation layer disposed over the contact pad, the passivation structure, and the protective layer;
a polymer layer disposed over the top passivation layer; and
a conductive pillar extending through the polymer layer and the top passivation layer to contact the contact pad,
wherein the top passivation layer and the protective layer comprise silicon nitride,
wherein the top passivation layer has a first density,
wherein the protective layer has a second density greater than the first density.
9 . The semiconductor structure of claim 8 , wherein a ratio of the second density to the first density is between about 2.5 and about 5.
10 . The semiconductor structure of claim 8 ,
wherein a thickness of the top passivation layer is between about 5 μm and about 15 μm,
wherein a thickness of the protective layer is between about 2 nm and about 2000 nm.
11 . The semiconductor structure of claim 8 , wherein the passivation structure includes:
a first passivation layer;
a metal-insulator-metal (MIM) capacitor disposed over and in contact with the first passivation layer; and
a second passivation layer disposed over and in contact with the MIM capacitor.
12 . The semiconductor structure of claim 11 ,
wherein the first passivation layer, the second passivation layer and the protective layer comprise silicon nitride,
wherein the first passivation layer and the second passivation layer have a first density,
wherein the protective layer has a second density greater than the first density.
13 . The semiconductor structure of claim 12 , wherein a ratio of the second density to the first density is between about 2.5 and about 5.
14 . A semiconductor structure, comprising:
a metal feature in a dielectric layer;
a passivation structure over the dielectric layer and the metal feature;
a contact pad over the passivation structure;
a plurality of contact vias extending through the passivation structure to electrically connect the metal feature and the contact pad;
a top passivation layer disposed over the contact pad and the passivation structure;
a polymer layer disposed over the top passivation layer; and
a conductive pillar extending through the polymer layer and the top passivation layer to contact the contact pad,
wherein the metal feature comprises a first thickness along a vertical direction,
wherein the contact pad comprises a second thickness along the vertical direction,
wherein the conductive pillar comprise a third thickness along the vertical direction,
wherein the third thickness is greater than the second thickness,
wherein the second thickness is greater than the first thickness.
15 . The semiconductor structure of claim 14 , wherein a ratio of the second thickness to the first thickness is between about 5 and about 10.
16 . The semiconductor structure of claim 14 , wherein a ratio of the third thickness to the second thickness is between about 1.5 and about 4.
17 . The semiconductor structure of claim 14 , wherein the passivation structure includes:
a first passivation layer;
a metal-insulator-metal (MIM) capacitor disposed over and in contact with the first passivation layer; and
a second passivation layer disposed over and in contact with the MIM capacitor.
18 . The semiconductor structure of claim 14 , wherein a bottom surface of the contact pad is spaced apart from the passivation structure by a barrier layer and a seed layer.
19 . The semiconductor structure of claim 5 ,
wherein the first passivation layer and the protective layer comprise silicon nitride,
wherein the first passivation layer has a first density,
wherein the protective layer has a second density greater than the first density.
20 . The semiconductor structure of claim 8 , further comprising:
a barrier layer disposed between the conductive pillar and the top passivation layer as well as between the conductive pillar and the polymer layer,
wherein the barrier layer comprises titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), or tungsten nitride (WN).