Semiconductor device and method of manufacturing the same

1 . A semiconductor device comprising:

at least one trench formed in an element formation region of a semiconductor substrate;

an insulating film formed on an inner wall of the at least one trench;

at least one p-type semiconductor portion embedded in a part of the at least one trench via the insulating film; and

at least one n-type semiconductor portion embedded in another part of the at least one trench via the insulating film and provided so as to contact with the at least one p-type semiconductor portion,

wherein the semiconductor substrate is a silicon substrate,

wherein the at least one n-type semiconductor portion has:

a first semiconductor portion into which arsenic is introduced; and

a second semiconductor portion into which phosphorus is introduced, and

wherein the first semiconductor portion is provided on and above the second semiconductor portion.

2 . The semiconductor device according to claim 1 ,

wherein the semiconductor substrate is a silicon substrate, and

wherein arsenic is introduced into the at least one n-type semiconductor portion.

3 . The semiconductor device according to claim 1 ,

wherein the semiconductor substrate is a silicon substrate, and

wherein boron is introduced into the at least one p-type semiconductor portion.

4 . The semiconductor device according to claim 1 ,

wherein the element formation region of the semiconductor substrate is provided with:

a power transistor; and

a temperature detection diode,

wherein the temperature detection diode includes:

the at least one p-type semiconductor portion embedded in the at least one trench; and

the at least one n-type semiconductor portion embedded in the at least one trench,

wherein the at least one p-type semiconductor portion is electrically connected to a first plug, and

wherein the at least one n-type semiconductor portion is electrically connected to a second plug.

5 . The semiconductor device according to claim 4 ,

wherein the semiconductor substrate is provided with a p-type layer,

wherein the power transistor is a trench gate type IGBT,

wherein the at least one trench is provided in the p-type layer and comprises a plurality of trenches,

wherein the plurality of trenches include:

a first trench;

a second trench provided next to the first trench, and

wherein a plug electrically connected to the p-type layer located between the first trench and the second trench is formed.

6 . The semiconductor device according to claim 5 ,

wherein the plug is connected to an emitter potential of the trench gate type IGBT via the p-type layer.

7 . The semiconductor device according to claim 1 ,

wherein the at least one p-type semiconductor portion comprises a plurality of p-type semiconductor portions,

wherein the at least one n-type semiconductor portion comprises a plurality of n-type semiconductor portions, and

wherein the plurality of p-type semiconductor portions and the plurality of n-type semiconductor portions are alternately arranged.

8 . The semiconductor device according to claim 7 ,

wherein the plurality of n-type semiconductor portions includes:

a first semiconductor portion connected to the first plug;

a second semiconductor portion connected to the second plug; and

a third semiconductor portion located between the first semiconductor portion and the second semiconductor portion.

9 . The semiconductor device according to claim 8 ,

wherein the semiconductor substrate is a silicon substrate,

wherein arsenic is introduced into the first semiconductor portion,

wherein arsenic is introduced into the second semiconductor portion, and

wherein phosphorus is introduced into the third semiconductor portion.

10 . The semiconductor device according to claim 8 ,

wherein an element formation region of the semiconductor substrate is provided with:

a power transistor having a gate electrode; and

a gate protection diode, and

wherein the gate protection diode includes:

the plurality of p-type semiconductor portions embedded in the at least one trench; and

the plurality of n-type semiconductor portions embedded in the at least one trench.

11 . The semiconductor device according to claim 10 ,

wherein the power transistor is a trench gate type IGBT,

wherein the first semiconductor portion is electrically connected to a gate electrode of the trench gate type IGBT via the first plug, and

wherein the second semiconductor portion is connected to an emitter potential of the trench gate type IGBT via the second plug.

12 . The semiconductor device according to claim 11 ,

wherein the at least one trench comprises a plurality of trenches,

wherein the plurality of trenches include:

a first trench; and

a second trench provided next to the first trench, and

wherein a plug connected to the emitter potential of the trench gate type IGBT is formed between the first trench and the second trench.

13 . A method of manufacturing a semiconductor device including a trench gate type power transistor, the method comprising:

(a) forming a gate trench in a first region of a semiconductor substrate, and forming a trench in a second region of the semiconductor substrate;

(b) forming a gate insulating film on an inner wall of the gate trench, and forming an insulating film on an inner wall of the trench;

(c) forming a gate electrode in the gate trench;

(d) forming a p-type semiconductor portion in the trench; and

(e) forming an n-type semiconductor portion contacting with the p-type semiconductor portion in the trench,

wherein the trench gate type power transistor is a trench gate type IGBT,

wherein the method comprises:

(f) forming an emitter region of the trench gate type IGBT; and

(g) forming a first plug electrically connected to the p-type semiconductor portion, and forming a second plug electrically connected to the n-type semiconductor portion,

wherein the (e) and the (f) are performed in the same step,

wherein the n-type semiconductor portion includes:

a first semiconductor portion; and

a second semiconductor portion, and

wherein the (e) has:

(e1) forming the first semiconductor portion in the same step as the (f); and

(e2) forming the second semiconductor portion in the same step as the (c).