High electron mobility transistor with gate electrode below the channel

1 . A low noise amplifier cryogenic quantum computing device, comprising:

a transistor structure configured to operate in a cryogenic environment, comprising:

a source electrode and drain electrode coupled to a top surface of a high-electron-mobility transistor (HEMT) heterostructure;

a gate electrode disposed beneath and in contact with an underside of the HEMT heterostructure, the gate electrode being encapsulated within an insulating material and electrically coupled through an encapsulated interconnect to a gate pad disposed on a top surface of the device; and

wherein the HEMT heterostructure comprises:

a first plurality of semiconductor layers;

a contact layer adjacent to the first plurality of semiconductor layers;

an intermediate semiconductor layer adjacent to the contact layer;

a channel layer adjacent to the intermediate semiconductor layer; and

a second plurality of semiconductor layers adjacent to the channel layer; and

wherein the first plurality of semiconductor layers, the contact layer, and the channel layer are comprised of materials selected to maintain carrier mobility at cryogenic temperatures.

2 . The device of claim 1 , wherein the gate electrode is coupled to an encapsulated electrical interconnect and the encapsulated electrical interconnect is coupled to a gate pad.

3 . The device of claim 1 , wherein the second plurality of semiconductor layers comprises:

a gate barrier layer adjacent to the channel layer; and

a semiconductor layer adjacent to the gate barrier layer.

4 . The device of claim 3 , wherein the gate electrode is in contact with the semiconductor layer of the underside of the HEMT heterostructure.

5 . The device of claim 1 , wherein the first plurality of semiconductor layers is removed to expose the contact layer.

6 . The device of claim 5 , wherein the source electrode and the drain electrode are coupled to the contact layer, wherein there is a gap in a center of the contact layer.

7 . The device of claim 1 , wherein the first plurality of semiconductor layers and the intermediate semiconductor layer comprise an indium phosphide binary semiconductor.

8 . The device of claim 1 , wherein the second plurality of semiconductor layers comprises an indium gallium arsenide alloy semiconductor.

9 . The device of claim 1 , further comprising:

one or more alignment markers located in contact with the underside of the HEMT heterostructure, the alignment markers configured to enable lithographic alignment after substrate inversion.

10 . A method, comprising:

coupling a source electrode and a drain electrode to a top surface of a high-electron-mobility transistor (HEMT) heterostructure; and

positioning a gate electrode in contact with an underside of the HEMT heterostructure, the gate electrode being encapsulated within an insulating material and electrically coupled through an encapsulated interconnect to a gate pad disposed on a top surface of the device; and

wherein the HEMT heterostructure comprises:

a first plurality of semiconductor layers;

a contact layer adjacent to the first plurality of semiconductor layers;

an intermediate semiconductor layer adjacent to the contact layer;

a channel layer adjacent to the intermediate semiconductor layer; and

a second plurality of semiconductor layers adjacent to the channel layer; and

wherein the first plurality of semiconductor layers, the contact layer, and the channel layer are comprised of materials selected to maintain carrier mobility at cryogenic temperatures.

11 . The method of claim 10 , further comprising:

coupling an electrical interconnect to the gate electrode, wherein the electrical interconnect and the gate electrode are encapsulated; and

coupling a gate pad to the electrical interconnect.

12 . The method of claim 10 , wherein the HEMT heterostructure comprises:

a first plurality of semiconductor layers;

a contact layer adjacent to the first plurality of semiconductor layers;

an intermediate semiconductor layer adjacent to the contact layer;

a channel layer adjacent to the intermediate semiconductor layer; and

a second plurality of semiconductor layers adjacent to the channel layer.

13 . The method of claim 12 , wherein the second plurality of semiconductor layers comprises:

a gate barrier layer adjacent to the channel layer; and

a semiconductor layer adjacent to the gate barrier layer.

14 . The method of claim 12 , further comprising:

removing the first plurality of semiconductor layers to expose the contact layer.

15 . The method of claim 14 , further comprising:

removing a center of the contact layer two create a first contact and a second contact, wherein the source electrode is coupled to the first contact and the drain electrode is coupled to the second contact.

16 . The method of claim 10 , further comprising:

positioning one or more alignment markers in contact with the underside of the HEMT heterostructure.

17 . A low noise amplifier cryogenic quantum computing device, comprising:

a transistor structure comprising:

a gate electrode; and

a semiconductor structure region comprising:

a barrier region on top of the gate electrode;

a channel region configured to carry a current on top of the barrier region;

a source electrode and a drain electrode located on top of the channel region;

wherein the gate electrode is encapsulated within an insulating material and electrically coupled through an encapsulated interconnect to a gate pad disposed on a top surface of the device; and

wherein the transistor structure comprises:

a first plurality of semiconductor layers;

a contact layer adjacent to the first plurality of semiconductor layers;

an intermediate semiconductor layer adjacent to the contact layer;

a channel layer adjacent to the intermediate semiconductor layer; and

a second plurality of semiconductor layers adjacent to the channel layer; and

wherein the first plurality of semiconductor layers, the contact layer, and the channel layer are comprised of materials selected to maintain carrier mobility at cryogenic temperatures.

18 . The device of claim 17 , wherein the gate electrode is coupled to an encapsulated electrical interconnect and the encapsulated electrical interconnect is coupled to a gate pad, wherein the encapsulated interconnect extends through the heterostructure to the gate pad, the interconnect being surrounded by an oxide encapsulation.

19 . The device of claim 17 , further comprising:

one or more alignment markers located under the barrier region, the alignment markers configured to facilitate lithographic alignment during fabrication of the cryogenic device.