Vertical MOSFET device
The present disclosure relates to a vertical MOSFET device, a manufacturing method and application thereof. The method includes: forming a first silicon layer, a first germanium-silicon layer, a second germanium-silicon layer, a third germanium-silicon layer and a second silicon layer that are vertically stacked from bottom to top on a substrate, where molar contents of germanium in the first germanium-silicon layer and the third germanium-silicon layer are both greater than the content of germanium in the second germanium-silicon layer; etching to form a nano stack structure; selectively etching the first germanium-silicon layer and the third germanium-silicon layer to form a first groove and a third groove; forming inner spacers of an extension region in the first groove and the third groove; selectively etching the second germanium-silicon layer to form a gate groove; forming a dummy gate in the gate groove; forming sources/drains; forming an active region with a shallow trench isolation layer; and removing the dummy gate to form a gate dielectric layer and a gate. The present disclosure can well control the size of channel, the size of inner spacers of the extension region, the size of the gates, and the like, and is applicable to either nanosheet or nanowire structures.
1 . A vertical MOSFET device, comprising a substrate, a source/drain, a first extension region, a channel, a second extension region, and a source/drain stacked from bottom to top on the substrate;
wherein gates are located on both sides of the channel, and the gates and the channel are isolated by gate dielectric; first inner spacers are located on both sides of the first extension region, second inner spacers are located on both sides of the second extension region, and the gates are located between the first inner spacers and the second inner spacers;
wherein the first extension region, the channel and the second extension region are all made of germanium-silicon material, and a molar content of germanium in the first extension region and a molar content of germanium in the second extension region are both greater than a content of germanium in the channel; and the sources/drains are silicon doped with ions; and
wherein the first extension region has the same thickness as the first inner spacers, the second extension region has the same thickness as the second inner spacers, the top and bottom surface of the first extension is the same as the top and bottom surface of the first inner spacer, the top and bottom surface of the second extension is the same as the top and bottom surface of the second inner spacer; and the outer sidewalls of the first inner spacers and the second inner spacers are substantially flush with the outer sidewalls of the source/drain.
2 . The vertical MOSFET device according to claim 1 , wherein the first inner spacers and the second inner spacers are made of silicon oxide.
3 . The vertical MOSFET device according to claim 1 , wherein the molar content of germanium in the first extension region and the molar content of germanium in the second extension region are the same, which is not less than 15%.
4 . The vertical MOSFET device according to claim 1 , wherein the molar content of germanium in the first extension region and the molar content of germanium in the second extension region are respectively 15% to 30%, and/or the molar content of germanium in the channel is 5% to 15%.
5 . The vertical MOSFET device according to claim 1 , wherein sidewalls of the sources/drains, sidewalls of the first inner spacers and sidewalls of the second inner spacers are connected with each other to form a groove, and the gates are located in the groove.
6 . The vertical MOSFET device according to claim 5 , wherein a width of the first inner spacers of the first extension region in a direction parallel to the channel is 5 nm to 15 nm, and/or a depth of the groove in a direction perpendicular to the channel is 5 nm to 25 nm.