3D-stacked semiconductor device including source/drain regions vertically isolated from each other by strengthened isolation structure
Provided is a semiconductor device which includes: a 1 st source/drain region connected to a 1 st channel structure; a 2 nd source/drain region, above the 1 st source/drain region, connected to a 2 nd channel structure above the 1 st channel structure; a channel isolation layer between the 1 st channel structure and the 2 nd channel structure; a source/drain isolation layer between the 1 st source/drain region and the 2 nd source/drain region; and a blocking structure between the channel isolation layer and the source/drain isolation layer, wherein an entire width of the blocking structure in a channel-length direction is vertically below a lateral edge portion of the 2 nd source/drain region.
1 . A semiconductor device comprising:
a 1 st source/drain region connected to a 1 st channel structure;
a 2 nd source/drain region, above the 1 st source/drain region, connected to a 2 nd channel structure above the 1 st channel structure;
a channel isolation layer between the 1 st channel structure and the 2 nd channel structure;
a source/drain isolation layer between the 1 st source/drain region and the 2 nd source/drain region; and
a blocking structure between the channel isolation layer and the source/drain isolation layer,
wherein an entire width of the blocking structure in a channel-length direction is vertically below a lateral edge portion of the 2 nd source/drain region, and
wherein the blocking structure is a physically non-monolithic structure.
2 . The semiconductor device of claim 1 , wherein a side surface of the blocking structure contacting the channel isolation layer is vertically aligned with a side surface of the 2 nd channel structure.
3 . The semiconductor device of claim 1 , wherein the blocking structure comprises a 1 st portion contacting the source/drain isolation layer and a 2 nd portion contacting the channel isolation layer, and
wherein the 1 st portion and the 2 nd portion have a structural boundary therebetween.
4 . The semiconductor device of claim 3 , wherein the 1 st and 2 nd portions of the blocking structure comprise a same material.
5 . The semiconductor device of claim 4 , wherein the same material comprises a silicon nitride.
6 . The semiconductor device of claim 5 , wherein the channel isolation layer and the source/drain isolation layer comprise different materials.
7 . The semiconductor device of claim 6 , wherein the channel isolation layer comprises a silicon nitride, and the source/drain isolation layer comprises a silicon oxide.
8 . The semiconductor device of claim 1 , further comprising a blocking layer on a top surface of the 1 st source/drain region,
wherein the blocking structure is formed above an end portion of the blocking layer.
9 . A semiconductor device comprising:
a 1 st source/drain region connected to a 1 st channel structure;
a 2 nd source/drain region, above the 1 st source/drain region, connected to a 2 nd channel structure above the 1 st channel structure;
a channel isolation layer between the 1 st channel structure and the 2 nd channel structure;
a source/drain isolation layer between the 1 st source/drain region and the 2 nd source/drain region; and
a blocking structure between the channel isolation layer and the source/drain isolation layer,
wherein the blocking structure comprises a 1 st portion and a 2 nd portion contacting each other with a physical interface therebetween.
10 . The semiconductor device of claim 9 , wherein the 1 st portion contacts the source/drain isolation layer, and the 2 nd portion contacts the channel isolation layer.
11 . The semiconductor device of claim 10 , wherein the 1 st and 2 nd portions of the blocking structure comprise a same material.
12 . The semiconductor device of claim 11 , wherein the same material comprises a silicon nitride.
13 . The semiconductor device of claim 9 , wherein an entire width of the blocking structure in a channel-length direction is vertically below a lateral edge portion of the 2 nd source/drain region.
14 . The semiconductor device of claim 13 , wherein the blocking structure is not vertically overlapped by the 1 st or 2 nd channel structure.
15 . A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor stack comprising a 1 st channel structure, a channel isolation layer and a 2 nd channel structure stacked in this order on a substrate;
forming a 1 st source/drain region based on the 1 st channel structure;
forming a blocking structure on a side surface of the channel isolation layer above a lateral edge portion of the 1 st source/drain region by multiple processes;
forming a 2 nd source/drain region based on the 2 nd channel structure from above the blocking structure; and
forming a source/drain isolation layer between the 1 st source/drain region and the 2 nd source/drain region,
wherein an entire width of the blocking structure in a channel-length direction is vertically below a lateral edge portion of the 2 nd source/drain region,
wherein the blocking structure comprises a 1 st portion and a 2 nd portion contacting each other with a structural boundary therebetween, and
wherein the 1 st portion is formed before the 1 st source/drain region is formed, and the 2 nd portion is formed after the 1 st source/drain region is formed.
16 . The method of claim 15 , further comprising forming an inner spacer on a side surface of the 2 nd channel structure such that a side surface of the inner spacer is vertically aligned with a side surface of the channel isolation layer, the inner spacer being configured to isolate a gate structure of the semiconductor device from the 2 nd source/drain region,
wherein the blocking structure is not vertically overlapped with the inner spacer.
17 . The method of claim 15 , wherein the 1 st and 2 nd portions of the blocking structure comprise a same material.
18 . The method of claim 17 , wherein the same material comprises a silicon nitride.