IP Library Granted Patent US 12707680
Granted Patent B2
US 12707680 · App. 17/617,015 · Granted Aug 11, 2026

Semiconductor device and method for manufacturing semiconductor device

Inventors: Shunpei Yamazaki (Setagaya, JP); Hiromi Sawai (Atsugi, JP); Hiroki Komagata (Atsugi, JP); Yasuhiro Jinbo (Isehara, JP); Naoki Okuno (Yamato, JP); Yoshihiro Komatsu (Ebina, JP); Motoharu Ando (Kobe, JP); Tomoaki Moriwaka (Isehara, JP); Koji Moriya (Atsugi, JP); Jun Ishikawa (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10D30/6755
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Quick Facts
Patent No.
US 12707680
App. No.
17/617,015
Granted
Aug 11, 2026
Kind
B2
Abstract

A semiconductor device with less variation in transistor characteristics is provided. The semiconductor device includes a semiconductor film, a pair of blocking films over the semiconductor film, and an insulating film provided over the semiconductor film and between the pair of blocking films. The semiconductor film includes a pair of n-type regions and an i-type region provided between the pair of n-type regions. The n-type regions overlap with the blocking films. The i-type region overlaps with the insulating film.

Claims (73)

1 . A semiconductor device comprising:

a first oxide;

a first conductor and a second conductor over the first oxide;

a second oxide between the first oxide and the first conductor;

a third oxide between the first oxide and the second conductor;

a first insulator comprising a first opening reaching the first oxide;

a second insulator over and in direct contact with the first oxide; and

a third conductor over the second insulator,

wherein the third conductor is positioned to fill the first opening between the first conductor and the second conductor with the second insulator therebetween,

wherein a side surface of the second oxide is in contact with a first side surface of the second insulator,

wherein a side surface of the third oxide is in contact with a second side surface of the second insulator,

wherein the first oxide comprises a first n-type region, a second n-type region, and an i-type region between the first n-type region and the second n-type region,

wherein the first n-type region overlaps with the first conductor and the second oxide,

wherein the second n-type region overlaps with the second conductor and the third oxide,

wherein the i-type region overlaps with the second insulator, and

wherein each of the second oxide and the third oxide is configured to inhibit passage of oxygen.

2 . The semiconductor device according to claim 1 ,

wherein each of the first conductor and the second conductor is configured to block an electromagnetic wave of greater than or equal to 300 MHz and less than or equal to 300 GHz.

3 . The semiconductor device according to claim 1 ,

wherein each of the first conductor and the second conductor comprises tantalum and nitrogen.

4 . The semiconductor device according to claim 1 ,

wherein the i-type region has a carrier concentration of higher than or equal to 1×10 −9 cm −3 and lower than 1×10 17 cm −3 , and

wherein each of the first n-type region and the second n-type region has a carrier concentration of higher than or equal to 1×10 17 cm −3 and lower than or equal to 1×10 21 cm −3 .

5 . The semiconductor device according to claim 1 ,

wherein the first oxide comprises a metal oxide.

6 . The semiconductor device according to claim 1 ,

wherein the first oxide comprises at least one of In, Ga, and Zn.

7 . The semiconductor device according to claim 1 ,

wherein the second insulator comprises silicon and oxygen.

8 . The semiconductor device according to claim 1 , further comprising:

a third insulator in direct contact with a first side surface of the first oxide, a side surface of the second oxide, and a side surface of the first conductor; and

a fourth insulator in direct contact with a second side surface of the first oxide, a side surface of the third oxide, and a side surface of the second conductor.

9 . The semiconductor device according to claim 1 , further comprising:

a second opening reaching the first conductor in the first insulator;

a third opening reaching the second conductor in the first insulator;

a third insulator in direct contact with an inner wall of the second opening; and

a fourth insulator in direct contact with an inner wall of the third opening,

wherein the third insulator and the fourth insulator are configured to inhibit diffusion of oxygen.

10 . A semiconductor device comprising:

a first oxide;

a first conductor and a second conductor over the first oxide;

a first insulator over the first conductor and the second conductor;

a second insulator over and in direct contact with the first insulator;

a third insulator over and in direct contact with the first oxide and between and in contact with the first conductor and the second conductor, the third insulator being in direct contact with a side surface of the first insulator, a side surface of the second insulator, a side surface of the first conductor, a side surface of the second conductor, and a top surface and a side surface of the first oxide; and

a fourth insulator over and in direct contact with a top surface and a side surface of the third insulator,

wherein the first oxide comprises a first n-type region, a second n-type region, and an i-type region between the first n-type region and the second n-type region,

wherein the first n-type region overlaps with the first conductor, the first insulator, and the second insulator,

wherein the second n-type region overlaps with the second conductor, the first insulator, and the second insulator,

wherein the i-type region overlaps with the third insulator, and

wherein each of the first insulator and the fourth insulator is configured to inhibit diffusion of oxygen.

11 . The semiconductor device according to claim 10 ,

wherein the first insulator comprises aluminum and oxygen.

12 . The semiconductor device according to claim 10 ,

wherein each of the first conductor and the second conductor is configured to block an electromagnetic wave of greater than or equal to 300 MHz and less than or equal to 300 GHz.

13 . The semiconductor device according to claim 10 ,

wherein each of the first conductor and the second conductor comprises tantalum and nitrogen.

14 . The semiconductor device according to claim 10 ,

wherein the i-type region has a carrier concentration of higher than or equal to 1×10 −9 cm −3 and lower than 1×10 17 cm −3 , and

wherein each of the first n-type region and the second n-type region has a carrier concentration of higher than or equal to 1×10 17 cm −3 and lower than or equal to 1×10 21 cm −3 .

15 . The semiconductor device according to claim 10 ,

wherein the first oxide comprises a metal oxide.

16 . The semiconductor device according to claim 10 ,

wherein the first oxide comprises at least one of In, Ga, and Zn.

17 . The semiconductor device according to claim 10 ,

wherein the second insulator comprises silicon and oxygen.

18 . The semiconductor device according to claim 10 ,

wherein the third insulator comprises silicon and oxygen.

19 . The semiconductor device according to claim 10 , further comprising:

a first opening reaching the first conductor in the first insulator and the second insulator;

a second opening reaching the second conductor in the first insulator and the second insulator;

a fifth insulator in direct contact with an inner wall of the first opening; and

a sixth insulator in direct contact with an inner wall of the second opening,

wherein the fifth insulator and the sixth insulator are configured to inhibit diffusion of oxygen.