Multigate transistors with capping layers and a buffer layer comprising germanium

1 . A semiconductor structure, comprising:

a substrate;

a structure extending from the substrate and comprising:

a base portion formed from the substrate,

a buffer layer disposed over the base portion, and

a plurality of nanostructures disposed over the buffer layer, wherein each of the plurality of nanostructures comprises a channel layer sandwiched between two cap layers along a direction perpendicular to the substrate;

an isolation feature disposed over the substrate and interfacing sidewalls of the base portion and sidewalls of the buffer layer; and

a gate structure wrapping around each of the plurality of nanostructures,

wherein the buffer layer comprises undoped germanium.

2 . The semiconductor structure of claim 1 , wherein a composition of the channel layer is different from a composition of the two cap layers.

3 . The semiconductor structure of claim 1 , wherein the channel layer and the two cap layers comprise germanium and tin.

4 . The semiconductor structure of claim 3 , wherein a first germanium content of the channel layer is smaller than a second germanium content of the two cap layers.

5 . The semiconductor structure of claim 4 ,

wherein the first germanium content is between about 87% and about 93%,

wherein the second germanium content is between about 95% and about 99.5%.

6 . The semiconductor structure of claim 3 , wherein a first tin content of the channel layer is greater than a second tin content of the two cap layers.

7 . The semiconductor structure of claim 6 ,

wherein the first tin content is between about 7% and about 13%,

wherein the second tin content is between about 0.5% and about 5%.

8 . The semiconductor structure of claim 1 , further comprising:

a plurality of inner spacer features interleaving the plurality of nanostructures, wherein each of the plurality of inner spacer features is spaced apart from the channel layer of one of the plurality of nanostructures by one of the two cap layers along the direction.

9 . A semiconductor structure, comprising:

a first source/drain feature and a second source/drain feature disposed over a substrate;

a plurality of channel members extending between the first source/drain feature and the second source/drain feature, wherein each of the plurality of channel members comprises a semiconductor layer sandwiched between two cap layers along a direction perpendicular to the substrate; and

a gate structure wrapping around each of the plurality of channel members,

wherein the gate structure interfaces the two cap layers of each of the plurality of channel members,

wherein the substrate comprises a buried oxide layer,

wherein the semiconductor layer and the two cap layers comprise germanium and tin,

wherein a first germanium content of the semiconductor layer is smaller than a second germanium content of the two cap layers.

10 . The semiconductor structure of claim 9 , wherein each of the first source/drain feature and the second source/drain feature is in direct contact with the semiconductor layer and the two cap layers of each of the plurality of channel members.

11 . The semiconductor structure of claim 9 , wherein a first tin content of the semiconductor layer is greater than a second tin content of the two cap layers.

12 . The semiconductor structure of claim 9 , wherein the first source/drain feature and the second source/drain feature comprise germanium, tin, boron, phosphorus, or arsenic.

13 . The semiconductor structure of claim 9 , further comprising:

a germanium buffer layer over the substrate and spaced apart from the buried oxide layer,

wherein the first source/drain feature, the second source/drain feature, and the gate structure are disposed on the germanium buffer layer.

14 . The semiconductor structure of claim 9 , further comprising:

an isolation feature over the substrate,

wherein the isolation feature interfaces a sidewall of the buried oxide layer.

15 . The semiconductor structure of claim 13 , wherein the first source/drain feature and the second source/drain feature partially extend into the germanium buffer layer.

16 . A semiconductor structure, comprising:

a substrate;

a buffer layer over the substrate;

a first source/drain feature and a second source/drain feature disposed over the substrate and partially extending into the buffer layer;

a plurality of channel members extending between the first source/drain feature and the second source/drain feature; and

a gate structure wrapping around each of the plurality of channel members,

wherein at least one of the plurality of channel members comprises a semiconductor layer sandwiched between two cap layers along a direction perpendicular to the substrate,

wherein the buffer layer comprises undoped germanium.

17 . The semiconductor structure of claim 16 , wherein the gate structure interfaces the two cap layers.

18 . The semiconductor structure of claim 16 ,

wherein each of the first source/drain feature and the second source/drain feature comprises:

a first epitaxial layer interfacing the plurality of channel members and the buffer layer, and

a second epitaxial layer spaced apart from the plurality of channel members and the buffer layer by the first epitaxial layer, and

wherein a composition of the first epitaxial layer is different from a composition of the second epitaxial layer.

19 . The semiconductor structure of claim 16 , wherein the semiconductor layer and the two cap layers comprise germanium and tin.

20 . The semiconductor structure of claim 18 ,

wherein a first germanium content of the semiconductor layer is smaller than a second germanium content of the two cap layers,

wherein a first tin content of the semiconductor layer is greater than a second tin content of the two cap layers.