Semiconductor structure and manufacturing method thereof

1 . A method, comprising:

doping a substrate to form a first well region and a second well region having a different conductivity type than the first well region;

forming a first fin structure upwardly extending above the first well region and a second fin structure upwardly extending above the second well region;

forming an isolation region between the first fin structure and the second fin structure;

forming a first gate electrode surrounding the first fin structure and a second gate electrode surrounding the second fin structure;

forming first source/drain regions adjoining the first fin structure and on opposite sides of the first gate electrode and second source/drain regions adjoining the second fin structure on opposite sides of the second gate electrode; and

forming an isolation line interposing the first gate electrode and the second gate electrode and laterally between a first one of the first source/drain regions and a first one of the second source/drain regions, the isolation line extending toward the substrate to a depth at least as deep as a depth of a bottommost surface of the isolation region, a bottommost surface of the isolation line overlying an interface between the first well region and the second well region, wherein forming the isolation line comprises, in a same deposition operation, depositing a dielectric material of the isolation line between the first gate electrode and the second gate electrode and between the first one of the first source/drain regions and the first one of the second source/drain regions.

2 . The method of claim 1 , wherein the isolation line is further laterally between a second one of the first source/drain regions and a second one of the second source/drain regions.

3 . The method of claim 1 , further comprising:

forming a third gate electrode surrounding the first fin structure and a fourth gate electrode surrounding the second fin structure, the isolation line further interposing the third gate electrode and the fourth gate electrode.

4 . The method of claim 1 , further comprising:

forming a first dielectric-base dummy gate on the first well region and a second dielectric-base dummy gate on the second well region, the isolation line further interposing the first dielectric-base dummy gate and the second dielectric-base dummy gate.

5 . The method of claim 1 , wherein the isolation line has a top surface level with top surfaces of the first gate electrode and the second gate electrode.

6 . The method of claim 1 , further comprising:

forming a gate contact extending from the first gate electrode across the isolation line to the second gate electrode.

7 . The method of claim 6 , further comprising:

forming a gate via on the gate contact and overlapping the isolation line.

8 . The method of claim 1 , further comprising:

forming a source/drain contact extending from the first one of the first source/drain regions across the isolation line to the first one of the second source/drain regions.

9 . The method of claim 1 , wherein forming the isolation region comprises:

forming a shallow trench isolation (STI) structure laterally surrounding lower portions of the first fin structure and the second fin structure.

10 . The method of claim 1 , wherein forming the isolation region comprises:

forming a shallow trench isolation (STI) structure laterally surrounding lower portions of the first fin structure and the second fin structure, the isolation line having a bottom end downwardly extending through the STI structure and having the bottommost surface contiguous with an upper surface of the first well region and an upper surface of the second well region.

11 . A method, comprising:

forming a first fin structure of a first circuit and a second fin structure of a second circuit upwardly extending above a substrate, the first fin structure positioned adjacent the second fin structure along a first direction;

forming a first gate electrode surrounding the first fin structure and a second gate electrode surrounding the second fin structure, the first gate electrode positioned adjacent the second gate electrode along the first direction;

forming first source/drain regions adjoining the first fin structure and on opposite sides of the first gate electrode along a second direction different than the first direction and second source/drain regions adjoining the second fin structure and on opposite sides of the second gate electrode along the second direction from a cross sectional view;

forming a first dielectric line isolating the first gate electrode from the second gate electrode along the first direction, the first dielectric line extending lengthwise along the second direction, the first dielectric line overlying a cell boundary between the first circuit and the second circuit, the first dielectric line having:

a first portion extending between the first gate electrode and the second gate electrode along the first direction, the first portion contacting a first longitudinal end of the first gate electrode and a second longitudinal end of the second gate electrode from a top view; and

a second portion extending between one of the first source/drain regions and one of the second source/drain regions along the first direction, the second portion adjacent the first portion along the second direction;

wherein the first portion has a first upper surface at a first elevation relative to an upper surface of the first gate electrode, and a first lower surface at a second elevation relative to an upper surface of a first well region in the substrate under the first fin structure;

wherein the second portion has a second upper surface at a third elevation different than the first elevation, and a second lower surface at a fourth elevation; and

forming a second dielectric line in the first circuit and offset from the first dielectric line along the first direction, the second dielectric line extending lengthwise along the second direction, an upper surface of the second dielectric line being at the first elevation.

12 . The method of claim 11 , wherein the first circuit is one of an NAND circuit, an inverter circuit, and an NOR circuit, and the second circuit is another one of the NAND circuit, the inverter circuit, and the NOR circuit.

13 . The method of claim 11 , further comprising:

forming a third fin structure of the first circuit upwardly extending above the substrate; and

forming a third gate electrode surrounding the third fin structure, wherein the dielectric line interposes the longitudinal end of the first gate electrode and a longitudinal end of the third gate electrode from the top view.

14 . The method of claim 11 , further comprising:

forming a third fin structure of a third circuit upwardly extending above the substrate;

forming a third gate electrode surrounding the third fin structure; and

forming third source/drain regions adjoining the third fin structure and on opposite sides of the third gate electrode from the cross sectional view, wherein the dielectric line extends past and contacts a longitudinal end of the third gate electrode from the top view.

15 . The method of claim 11 , further comprising:

forming a dielectric-base dummy gate on the substrate and in parallel with the first gate electrode, wherein the dielectric line extends past and contacts a longitudinal end of the dielectric-base dummy gate from the top view.

16 . The method of claim 15 , wherein the dielectric-base dummy gate is laterally between the first gate electrode and the second gate electrode.

17 . The method of claim 15 , wherein the first gate electrode is laterally between the second gate electrode and the dielectric-base dummy gate.

18 . A method, comprising:

forming a p-type transistor on a substrate, comprising:

forming a first stack comprising a first channel layer and a second channel layer arranged over a first fin in a first direction substantially perpendicular to a top surface of the substrate;

forming a first gate electrode extending along a second direction and wrapping around the first channel layer; and

forming first source/drain regions above the substrate, wherein the first channel layer and the second channel layer extend in a third direction between the first source/drain regions;

forming an n-type transistor on the substrate, comprising:

forming a second stack comprising a third channel layer and a fourth channel layer arranged over a second fin in the first direction substantially perpendicular to the top surface of the substrate;

forming a second gate electrode extending along the second direction and wrapping around the third channel layer; and

forming second source/drain regions above the substrate, wherein the third channel layer and the fourth channel layer extend in the third direction between the second source/drain regions;

forming an isolation region extending along the second direction between the first fin and the second fin;

forming a dielectric strip extending between the p-type transistor and the n-type transistor from a top view, the dielectric strip extending toward the substrate to a depth at least as deep as depth of a bottommost surface of the isolation region; and

forming a gate contact extending from the first gate electrode across the dielectric strip to the second gate electrode from the top view.

19 . The method of claim 18 , wherein forming the gate contact comprises forming the gate contact to contact with the dielectric strip.

20 . The method of claim 18 , further comprising:

forming a gate via on the gate contact and overlapping the dielectric strip.