Semiconductor structure and manufacturing method thereof

1 . A method, comprising:

forming a transistor comprising a channel region, a gate structure surrounding the channel region, and a plurality of source/drain regions on opposite sides of the gate structure;

forming a front-side contact on a front-side of one of the source/drain regions;

forming a back-side conductive via below the one of the source/drain regions, wherein the front-side contact further downwardly extends from the front-side of the one of the source/drain regions to the back-side conductive via, wherein the one of the source/drain regions is in contact with the back-side conductive via; and

forming a back-side power supply voltage line connecting to the back-side conductive via.

2 . The method of claim 1 , comprising:

forming an isolation structure, wherein a lower portion of the one of the source/drain regions is formed adjacent the isolation structure; and

removing material of the isolation structure to expose a bottom surface of the front-side contact, a bottom surface of the one of the source/drain regions, and a bottom surface of the gate structure;

wherein forming the back-side conductive via comprises forming the back-side conductive via having an upper surface contiguous with the bottom surface of the front-side contact, the bottom surface of the one of the source/drain regions, and a bottom surface of the isolation structure.

3 . The method of claim 1 , further comprising:

forming a back-side dielectric layer sandwiched between the one of the source/drain regions and the back-side conductive via, the front-side contact passing through the back-side dielectric layer and being in contact with the back-side conductive via.

4 . The method of claim 1 , further comprising:

forming a front-side power supply voltage line electrically connecting to the front-side contact.

5 . The method of claim 4 , further comprising:

forming a front-side conductive via landing on the front-side contact, the front-side power supply voltage line being in contact with the front-side conductive via.

6 . The method of claim 1 , wherein the front-side contact is free from being in contact with conductive vias.

7 . The method of claim 1 , further comprising:

forming a shallow trench isolation (STI) structure laterally surrounding a lower portion of the one of the source/drain regions, the front-side contact passing through the STI structure and being in contact with the back-side conductive via.

8 . The method of claim 1 , wherein the one of the source/drain regions comprises an n-type dopant, an upper portion of the one of the source/drain regions having a higher n-type dopant concentration than a lower portion of the one of the source/drain regions.

9 . The method of claim 1 , wherein the one of the source/drain regions comprises a p-type dopant, an upper portion of the one of the source/drain regions having a higher p-type dopant concentration than a lower portion of the one of the source/drain regions.

10 . The method of claim 1 , wherein the transistor is a vertically stacked multiple channels gate all around transistor.

11 . A method, comprising:

forming a plurality of first nanostructures arranged in a vertical direction;

forming a gate strip surrounding each of the first nanostructures;

growing a plurality of first epitaxial structures on either side of each of the first nanostructures;

forming a dielectric layer over the first epitaxial structures;

forming a first contact in the dielectric layer, wherein one of the first epitaxial structures is partially embedded in a back-side of the first contact;

forming a first conductive via underlying the one of the first epitaxial structures, the first conductive via being in contact with the back-side of the first contact and having an upper surface contiguous with a bottom surface of the one of the first epitaxial structures; and

forming a first power supply voltage line in contact with a back-side of the first conductive via.

12 . The method of claim 11 , further comprising:

forming a second power supply voltage line above the dielectric layer, the second power supply voltage line being electrically connecting to the first contact.

13 . The method of claim 11 , further comprising:

forming a plurality of second nanostructures arranged in the vertical direction, wherein the gate strip further surrounds each of the second nanostructures;

growing a plurality of second epitaxial structures on either side of each of the second nanostructures; and

forming a second contact in the dielectric layer, wherein one of the second epitaxial structures is partially embedded in the second contact.

14 . The method of claim 13 , further comprising:

forming a second conductive via underlying the one of the second epitaxial structures, the second conductive via being in contact with a back-side of the second contact.

15 . The method of claim 11 , wherein the first contact has a greater height than the one of the first epitaxial structures.

16 . The method of claim 11 , wherein the first nanostructures, the gate strip, and the first epitaxial structures form an inverter circuit, an NAND circuit, an NOR circuit, an AND circuit, an OR circuit, a flip-flop circuit, or a SCAN circuit.

17 . A method, comprising:

forming a plurality of nanostructures arranged in a first direction;

forming a source/drain region adjacent the plurality of nanostructures along a second direction different than the first direction;

forming a contact layer around the source/drain region, the contact layer extending from above the source/drain region to below the source/drain region; and

forming a conductive via having an upper surface contiguous with a bottom surface of the contact layer;

prior to forming the conductive via, forming a back-side dielectric on the bottom surface of the contact layer and a bottom surface of the source/drain region; and

thinning a portion of the back-side dielectric underlying the source/drain region;

wherein forming the conductive via comprises forming the conductive via underlying the source/drain region and separated from the source/drain region by the back-side dielectric.

18 . The method of claim 17 , wherein:

forming the back-side dielectric comprises forming the back-side dielectric on a bottom surface of an isolation structure positioned adjacent the source/drain region.

19 . The method of claim 18 , wherein forming the contact layer comprises:

removing a second isolation structure positioned adjacent the source/drain region, yielding an opening; and

forming the contact layer in the opening.

20 . The method of claim 17 , further comprising:

forming a front-side conductive via overlying the contact layer; and

forming a power supply voltage line overlying the front-side conductive via, the power supply voltage line being electrically coupled to the conductive via through the contact layer.