IP Library Granted Patent US 12707688
Granted Patent B2
US 12707688 · App. 17/821,165 · Granted Aug 11, 2026

Semiconductor structure with roughened sidewall and method of manufacturing thereof

Inventor: Jen-Yuan Chang (Hsinchu City, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
H10D62/50H10W90/00H10W90/732
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Quick Facts
Patent No.
US 12707688
App. No.
17/821,165
Granted
Aug 11, 2026
Kind
B2
Abstract

A semiconductor structure includes a die structure including: a substrate having a sidewall; a dielectric disposed over the substrate; an interconnect structure disposed within the dielectric; and a capping member surrounding the die structure, wherein the sidewall of the substrate includes a plurality of recesses extending into the substrate, and each of the plurality of recesses surrounds at least a portion of the capping member.

Claims (42)

1 . A semiconductor structure, comprising:

a die structure including:

a substrate having a first sidewall and a first surface coupled to and substantially orthogonal to the first sidewall;

a dielectric disposed over the substrate and having a second sidewall coupled to the first sidewall and the first surface and substantially coplanar with the first sidewall;

an interconnect structure disposed within the dielectric; and

a capping member surrounding the die structure,

wherein the first sidewall of the substrate includes a plurality of recesses extending into the substrate, each of the plurality of recesses surrounds at least a portion of the capping member, and the capping member contacts the first sidewall and the second sidewall.

2 . The semiconductor structure of claim 1 , wherein the capping member includes a plurality of protrusions complementary with the plurality of recesses of the sidewall of the substrate respectively.

3 . The semiconductor structure of claim 2 , wherein the plurality of protrusions of the capping member are spaced apart from each other in a distance of substantially greater than 0.1 um.

4 . The semiconductor structure of claim 1 , wherein the first sidewall of the substrate includes a plurality of protrusions alternately disposed with the plurality of recesses.

5 . The semiconductor structure of claim 1 , wherein each of the plurality of recesses has a depth of substantially greater than 0.5 um, and has a width of substantially greater than 0.1 um.

6 . The semiconductor structure of claim 1 , wherein the capping member includes organic polymeric material.

7 . The semiconductor structure of claim 1 , wherein the capping member includes a first layer contacting the die structure, and a second layer conformal to the first layer.

8 . The semiconductor structure of claim 6 , wherein the first layer is conformal to the entire first sidewall of the substrate.

9 . The semiconductor structure of claim 1 , wherein the die structure further includes:

a bonding dielectric disposed over the dielectric of the die structure and surrounded by the capping member; and

a bonding pad disposed over the dielectric of the die structure, coupled with the interconnect structure, and surrounded by the bonding dielectric.

10 . The semiconductor structure of claim 9 , wherein the capping member is in contact with the bonding dielectric, the dielectric and the substrate.

11 . A semiconductor structure, comprising:

a die structure including:

a substrate having a first surface, a second surface opposite to the first surface, and a first sidewall extending between the first surface and the second surface;

a dielectric disposed over the first surface of the substrate and having a second sidewall;

an interconnect structure disposed within the dielectric; and

a capping member surrounding the die structure,

wherein a first interior angle between the first surface and the first sidewall of the substrate is an obtuse angle or an acute angle, wherein a second interior angle between the first surface and the second sidewall is different from the first interior angle, and the first sidewall is not in parallel to the second sidewall.

12 . The semiconductor structure of claim 11 , wherein the sidewall of the substrate is a slanted sidewall.

13 . The semiconductor structure of claim 11 , wherein the sidewall of the substrate is convex sidewall or concave sidewall.

14 . The semiconductor structure of claim 11 , wherein the substrate is protruded into the capping member.

15 . The semiconductor structure of claim 11 , wherein the capping member is protruded into the substrate.

16 . A semiconductor structure, comprising:

a die structure including:

a substrate;

a dielectric disposed over the substrate; and

an interconnect structure surrounded by the dielectric; and

a capping member in contact with the die structure,

wherein the capping member includes a first layer at least partially extending into a plurality of recesses indented into a sidewall of the substrate, and a second layer conformal to the first layer,

the plurality of recesses surround at least a portion of the second layer of the capping member,

and the second layer is separated from the substrate and the dielectric by the first layer.

17 . The semiconductor structure of claim 16 , wherein the plurality of recesses are spaced from each other in a distance substantially greater than 0.1 um.

18 . The semiconductor structure of claim 16 , further comprising a die pad between the substrate and the dielectric and electrically connected to the interconnect structure.

19 . The semiconductor structure of claim 16 , wherein a ratio of carbon to fluorine of the first layer is different from a ratio of carbon to fluorine of the second layer.

20 . The semiconductor structure of claim 16 , wherein the capping member includes a plurality of protrusions complementary with the plurality of recesses of the substrate.