Gate-all-around (GAA) device including a superlattice
A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, and a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
1 . A semiconductor gate-all-around (GAA) device comprising:
spaced apart source and drain regions;
a plurality of semiconductor nanosheets extending between the source and drain regions;
a gate surrounding the plurality of semiconductor nanosheets in a gate-all-around arrangement; and
at least one superlattice within at least one of the nanosheets, the at least one superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
2 . The semiconductor GAA device of claim 1 wherein the at least one non-semiconductor monolayer in a first group of layers of the superlattice comprises oxygen and is devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice comprises carbon.
3 . The semiconductor GAA device of claim 2 wherein the second group of layers is above the first group of layers in the superlattice.
4 . The semiconductor GAA device of claim 2 wherein the second group of layers of the superlattice comprises carbon and is devoid of oxygen.
5 . The semiconductor GAA device of claim 2 wherein the second group of layers of the superlattice comprises carbon and oxygen.
6 . The semiconductor GAA device of claim 1 wherein the at least one superlattice comprises first and second vertically spaced-apart superlattices within the at least one semiconductor nanosheet.
7 . The semiconductor GAA device of claim 1 wherein the at least one superlattice is vertically centered within the at least one semiconductor nanosheet.
8 . The semiconductor GAA device of claim 1 further comprising spaced shallow trench isolation (STI) regions adjacent the source and drain regions.
9 . The semiconductor GAA device of claim 1 wherein the base semiconductor portion comprises silicon.
10 . A semiconductor gate-all-around (GAA) device comprising:
spaced apart source and drain regions;
a plurality of semiconductor nanosheets extending between the source and drain regions;
a gate surrounding the plurality of semiconductor nanosheets in a gate-all-around arrangement; and
a superlattice vertically centered within each of the nanosheets, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
the at least one non-semiconductor monolayer in a first group of layers of the superlattice comprising oxygen and devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice comprising carbon.
11 . The semiconductor GAA device of claim 10 wherein the second group of layers is above the first group of layers in the superlattice.
12 . The semiconductor GAA device of claim 10 wherein the second group of layers of the superlattice comprises carbon and is devoid of oxygen.
13 . The semiconductor GAA device of claim 10 wherein the second group of layers of the superlattice comprises carbon and oxygen.
14 . The semiconductor GAA device of claim 10 further comprising spaced shallow trench isolation (STI) regions adjacent the source and drain regions.
15 . The semiconductor GAA device of claim 10 wherein the base semiconductor portion comprises silicon.
16 . A semiconductor gate-all-around (GAA) device comprising:
spaced apart source and drain regions;
a plurality of semiconductor nanosheets extending between the source and drain regions;
a gate surrounding the plurality of semiconductor nanosheets in a gate-all-around arrangement; and
first and second vertically spaced-apart superlattices within the at least one semiconductor nanosheet, each of the first and second superlattices comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
the at least one non-semiconductor monolayer in a first group of layers of the superlattice comprising oxygen and devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice comprising carbon.
17 . The semiconductor GAA device of claim 16 wherein the second group of layers is above the first group of layers in the superlattice.
18 . The semiconductor GAA device of claim 16 wherein the second group of layers of the superlattice comprises carbon and is devoid of oxygen.
19 . The semiconductor GAA device of claim 16 wherein the second group of layers of the superlattice comprises carbon and oxygen.
20 . The semiconductor GAA device of claim 16 further comprising spaced shallow trench isolation (STI) regions adjacent the source and drain regions.
21 . The semiconductor GAA device of claim 16 wherein the base semiconductor portion comprises silicon.