IP Library Granted Patent US 12707692
Granted Patent B2
US 12707692 · App. 18/590,634 · Granted Aug 11, 2026

Contacts for semiconductor devices and methods of forming the same

Inventors: Te-Chih Hsiung (Taipei City, TW); Jyun-De Wu (New Taipei City, TW); Yi-Chen Wang (Zhubei City, TW); Yi-Chun Chang (Hsinchu, TW); Yuan-Tien Tu (Puzih City, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H10D62/83H10D30/6735H10D62/118H10D64/01H10D64/62H10P50/28H10P95/06H10W20/42
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Quick Facts
Patent No.
US 12707692
App. No.
18/590,634
Granted
Aug 11, 2026
Kind
B2
Abstract

Conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.

Claims (35)

1 . A semiconductor device comprising:

a first interlayer dielectric (ILD) layer over a transistor structure;

a first contact extending through the first ILD layer, the first contact being electrically coupled to a first source/drain region of the transistor structure, a top surface of the first contact being convex, the top surface of the first contact being below a top surface of the first ILD layer, the first contact comprising cobalt;

a second ILD layer over the first ILD layer and the first contact; and

a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact, the second contact comprising a butted contact, the second contact being electrically coupled with a gate electrode of the transistor structure.

2 . The semiconductor device of claim 1 , wherein a top surface of the second contact is convex.

3 . The semiconductor device of claim 2 , wherein the top surface of the second contact is disposed below a top surface of the second ILD layer.

4 . The semiconductor device of claim 2 , wherein the top surface of the first contact is 2 nm to 3 nm below the top surface of the first ILD layer.

5 . The semiconductor device of claim 1 , wherein the first contact is electrically coupled to the first source/drain region through a silicide region.

6 . The semiconductor device of claim 5 , wherein the silicide region comprises titanium silicide.

7 . The semiconductor device of claim 1 , further comprising a contact etch stop layer (CESL) between the first ILD layer and the second ILD layer.

8 . The semiconductor device of claim 7 , wherein the CESL conforms to the convex top surface of the first contact.

9 . A method comprising:

forming a first interlayer dielectric (ILD) layer over a transistor structure;

etching a first opening through the first ILD layer;

depositing a first contact in the first opening, wherein the first contact comprises cobalt;

planarizing the first ILD layer and the first contact, wherein a top surface of the first contact is below a top surface of the first ILD layer after planarizing; and

annealing the first contact in a hydrogen-containing atmosphere, wherein a top surface of the first contact is non-planar after annealing the first contact.

10 . The method of claim 9 , wherein the annealing is performed at a temperature greater than 100° C.

11 . The method of claim 9 , wherein the top surface of the first contact is disposed above the top surface of the first ILD layer after planarizing and before annealing.

12 . The method of claim 9 , wherein the top surface of the first contact is concave after planarizing and remains concave after annealing.

13 . The method of claim 9 , wherein the top surface of the first contact is flat after planarizing and becomes convex after annealing.

14 . The method of claim 9 , further comprising:

forming a second contact extending through a second ILD layer, wherein the second contact is electrically coupled with the first contact.

15 . The method of claim 9 , wherein after annealing the first contact, the top surface of the first contact is convex and disposed below the top surface of the first ILD layer.

16 . The method of claim 9 , wherein after annealing the first contact, the top surface of the first contact is convex and disposed above the top surface of the first ILD layer.

17 . A semiconductor device comprising:

a substrate having a transistor structure formed thereon;

a first interlayer dielectric (ILD) layer over the transistor structure;

a first contact extending through the first ILD layer and electrically coupled to a source/drain region of the transistor structure, the first contact having a convex top surface that is recessed relative to a top surface of the first ILD layer; and

a second ILD layer formed over the first ILD layer and the first contact; and

a second contact in the second ILD, the second contact being electrically coupled to the first contact.

18 . The semiconductor device of claim 17 , wherein the first contact comprises a metal selected from the group consisting of tungsten, copper, and aluminum.

19 . The semiconductor device of claim 17 , further comprising a silicide contact interface between the first contact and the source/drain region.

20 . The semiconductor device of claim 17 , wherein the second ILD layer comprises a low-k dielectric material.