IP Library › Granted Patent US 12707697
Granted Patent B2
US 12707697 · App. 18/381,442 · Granted Aug 11, 2026

Heterogeneous metal line compositions for advanced integrated circuit structure fabrication

Inventors: Andrew W. Yeoh (Portland, OR); Joseph Steigerwald (Forest Grove, OR); Jinhong Shin (Portland, OR); Vinay Chikarmane (Portland, OR); Christopher P. Auth (Portland, OR)
Assignee: Intel Corporation
H10D64/017H10B10/12H10D1/47H10D1/474H10D30/024H10D30/0245H10D30/62H10D30/6211H10D30/6213H10D30/6219H10D30/792H10D30/794H10D30/795H10D30/797H10D62/021H10D62/115H10D62/116H10D62/151H10D62/822H10D62/834H10D64/0112H10D64/01354H10D64/015H10D64/021H10D64/259H10D64/689H10D84/0151H10D84/0158H10D84/0167H10D84/017H10D84/0172H10D84/0177H10D84/0181H10D84/0186H10D84/0188H10D84/0193H10D84/038H10D84/834H10D84/853H10D84/856H10D89/10H10P14/27H10P14/3411H10P14/418H10P50/282H10P50/695H10P50/73H10P76/4085H10W10/014H10W10/0145H10W10/17H10W20/035H10W20/037H10W20/056H10W20/069H10W20/071H10W20/077H10W20/081H10W20/089H10W20/42H10W20/425H10W20/43H10W20/435H10W20/4403H10W20/48H10D30/0212H10D30/6212H10D30/791H10D84/0135H10D84/0149H10P14/69215H10P14/69433H10P76/405H10W20/063H10W74/15H10W90/724H10W90/734
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Quick Facts
Patent No.
US 12707697
App. No.
18/381,442
Granted
Aug 11, 2026
Kind
B2
Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

Claims (47)

1 . An integrated circuit structure, comprising:

a first plurality of conductive interconnect lines in and spaced apart by a first dielectric layer above a substrate, wherein individual ones of the first plurality of conductive interconnect lines have a longest dimension along a first direction, wherein individual ones of the first plurality of conductive interconnect lines have an uppermost surface above an uppermost surface of the first dielectric layer, and wherein individual ones of the first plurality of conductive interconnect lines comprise:

a first conductive fill material having sidewalls and a bottom, the first conductive fill material having a composition; and

a first conductive barrier material along the sidewalls and the bottom of the first conductive fill material, the first conductive barrier material in contact with the first dielectric layer and with the first conductive fill material, and the first conductive barrier material having a first composition; and

a second plurality of conductive interconnect lines in and spaced apart by a second dielectric layer above the first dielectric layer, wherein individual ones of the second plurality of conductive interconnect lines have a longest dimension along a second direction orthogonal to the first direction, and wherein individual ones of the second plurality of conductive interconnect lines comprise:

a second conductive fill material having sidewalls and a bottom, the second conductive fill material having a composition, the composition of the second conductive fill material different than the composition of the first conductive fill material; and

a second conductive barrier material along the sidewalls and the bottom of the second conductive fill material, the second conductive barrier material in contact with the second dielectric layer and with the second conductive fill material, and the second conductive barrier material having a second composition different than the first composition of the first conductive barrier material; and

a conductive via coupling one of the first plurality of conductive interconnect lines directly to one of the second plurality of conductive interconnect lines.

2 . The integrated circuit structure of claim 1 , wherein the composition of the first or second conductive fills comprise copper.

3 . The integrated circuit structure of claim 1 , wherein the composition of the first or second conductive fills comprise cobalt.

4 . The integrated circuit structure of claim 1 , wherein individual ones of the first plurality of conductive interconnect lines have a first width, and individual ones of the second plurality of conductive interconnect lines have a second width greater than the first width.

5 . The integrated circuit structure of claim 1 , wherein the first plurality of conductive interconnect lines has a first pitch, and the second plurality of conductive interconnect lines has a second pitch greater than the first pitch.

6 . The integrated circuit structure of claim 1 , wherein individual ones of the first plurality of conductive interconnect lines have a first width, and individual ones of the second plurality of conductive interconnect lines have a second width greater than the first width, and wherein the first plurality of conductive interconnect lines has a first pitch, and the second plurality of conductive interconnect lines has a second pitch greater than the first pitch.

7 . A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a first plurality of conductive interconnect lines in and spaced apart by a first dielectric layer above a substrate, wherein individual ones of the first plurality of conductive interconnect lines have a longest dimension along a first direction, wherein individual ones of the first plurality of conductive interconnect lines have an uppermost surface above an uppermost surface of the first dielectric layer, and wherein individual ones of the first plurality of conductive interconnect lines comprise:

a first conductive fill material having sidewalls and a bottom, the first conductive fill material having a composition; and

a first conductive barrier material along the sidewalls and the bottom of the first conductive fill material, the first conductive barrier material in contact with the first dielectric layer and with the first conductive fill material, and the first conductive barrier material having a first composition; and

a second plurality of conductive interconnect lines in and spaced apart by a second dielectric layer above the first dielectric layer, wherein individual ones of the second plurality of conductive interconnect lines have a longest dimension along a second direction orthogonal to the first direction, and wherein individual ones of the second plurality of conductive interconnect lines comprise:

a second conductive fill material having sidewalls and a bottom, the second conductive fill material having a composition, the composition of the second conductive fill material different than the composition of the first conductive fill material; and

a second conductive barrier material along the sidewalls and the bottom of the second conductive fill material, the second conductive barrier material in contact with the second dielectric layer and with the second conductive fill material, and the second conductive barrier material having a second composition different than the first composition of the first conductive barrier material; and

a conductive via coupling one of the first plurality of conductive interconnect lines directly to one of the second plurality of conductive interconnect lines.

8 . The computing device of claim 7 , further comprising:

a memory coupled to the board.

9 . The computing device of claim 7 , further comprising:

a communication chip coupled to the board.

10 . The computing device of claim 7 , further comprising:

a camera coupled to the board.

11 . The computing device of claim 7 , further comprising:

a battery coupled to the board.

12 . The computing device of claim 7 , further comprising:

an antenna coupled to the board.

13 . The computing device of claim 7 , wherein the component is a packaged integrated circuit die.

14 . The computing device of claim 7 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

15 . The computing device of claim 7 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set- top box.

16 . A method of fabricating an integrated circuit structure, the method comprising:

forming a first plurality of conductive interconnect lines in and spaced apart by a first dielectric layer above a substrate, wherein individual ones of the first plurality of conductive interconnect lines have a longest dimension along a first direction, wherein individual ones of the first plurality of conductive interconnect lines have an uppermost surface above an uppermost surface of the first dielectric layer, and wherein forming individual ones of the first plurality of conductive interconnect lines comprises:

forming a first conductive barrier material; and

forming a first conductive fill material having sidewalls and a bottom, the first conductive fill material having a composition, wherein the first conductive barrier material is along the sidewalls and the bottom of the first conductive fill material, the first conductive barrier material is in contact with the first dielectric layer and with the first conductive fill material, and the first conductive barrier material has a first composition; and

forming a second plurality of conductive interconnect lines in and spaced apart by a second dielectric layer above the first dielectric layer, wherein individual ones of the second plurality of conductive interconnect lines have a longest dimension along a second direction orthogonal to the first direction, wherein a conductive via couples one of the first plurality of conductive interconnect lines directly to one of the second plurality of conductive interconnect lines, and wherein forming individual ones of the second plurality of conductive interconnect lines comprises:

forming a second conductive barrier material; and

forming a second conductive fill material having sidewalls and a bottom, the second conductive fill material having a composition, the composition of the second conductive fill material different than the composition of the first conductive fill material, wherein the second conductive barrier material is along the sidewalls and the bottom of the second conductive fill material, the second conductive barrier material is in contact with the second dielectric layer and with the second conductive fill material, and the second conductive barrier material has a second composition different than the first composition of the first conductive barrier material.

17 . The method of claim 16 , wherein the composition of the first and second conductive fills comprise copper.

18 . The method of claim 16 , wherein the composition of the first and second conductive fills comprise cobalt.

19 . The method of claim 16 , wherein individual ones of the first plurality of conductive interconnect lines have a first width, and individual ones of the second plurality of conductive interconnect lines have a second width greater than the first width.

20 . The method of claim 16 , wherein the first plurality of conductive interconnect lines has a first pitch, and the second plurality of conductive interconnect lines has a second pitch greater than the first pitch.