Trench power device with enhanced charge carrier mobility
A power transistor device includes a semiconductor substrate, a gate trench extending into the semiconductor substrate, a transistor gate provided in the gate trench, and an insulating structure formed between the transistor gate and a side wall of the gate trench. The insulating structure is configured to electrically insulate the transistor gate from a channel region which extends along the side wall of the gate trench. The insulating structure includes a layer of piezoelectric material.
1 . A power transistor device, comprising:
a semiconductor substrate;
a gate trench extending into the semiconductor substrate;
a transistor gate provided in the gate trench; and
an insulating structure formed between the transistor gate and a side wall of the gate trench, the insulating structure being configured to electrically insulate the transistor gate from a channel region which extends along the side wall of the gate trench, the insulating structure comprising a layer of piezoelectric material,
wherein the insulating structure further comprises an insulating layer sandwiched between the side wall of the gate trench and the layer of piezoelectric material.
2 . The power transistor device of claim 1 , wherein the insulating structure further comprises an insulating layer sandwiched between the transistor gate and the layer of piezoelectric material.
3 . The power transistor device of claim 2 , wherein the insulating layer is a SiO 2 layer.
4 . The power transistor device of claim 1 , wherein the layer of piezoelectric material directly contacts the transistor gate.
5 . The power transistor device of claim 1 , wherein the insulating layer is a SiO 2 layer.
6 . The power transistor device of claim 1 , further comprising:
a body region in the semiconductor substrate;
a source or emitter region in the semiconductor substrate above the body region; and
a drift zone region in the semiconductor substrate below the body region.
7 . The power transistor device of claim 1 , further comprising:
a field plate in the gate trench below the transistor gate.
8 . The power transistor device of claim 7 , wherein the field plate is electrically insulated from the transistor gate, and wherein the layer of piezoelectric material extends between the transistor gate and the field plate.
9 . The power transistor device of claim 1 , further comprising:
a field plate provided in a field plate trench which is separate from the gate trench.
10 . The power transistor device of claim 1 , wherein the layer of piezoelectric material comprises Al(Sc)N or BaTiO 3 or Pb (Zr,Ti)O 3 or doped ZrO 2 .
11 . The power transistor device of claim 1 , wherein the layer of piezoelectric material is configured to enhance the mobility of charge carriers in the channel region by introducing strain into the channel region that occurs in an ON state of the power transistor device as a result of the converse piezoelectric effect.
12 . The power transistor device of claim 11 , wherein the layer of piezoelectric material is configured such that in an OFF state of the power transistor device, the strain introduced into the channel region in the ON state of the power transistor device disappears.
13 . The power transistor device of claim 1 , wherein the power transistor device is a trench power MOSFET or a trench power IGBT.
14 . A power transistor device, comprising:
a semiconductor substrate;
a gate trench extending into the semiconductor substrate;
a transistor gate provided in the gate trench;
a field plate provided in the gate trench below the transistor gate; and
an insulating structure formed between the field plate and a side wall of the gate trench, the insulating structure being configured to electrically insulate the field plate from a drift zone region which extends along the side wall of the gate trench, the insulating structure comprising a layer of piezoelectric material.
15 . The power transistor device of claim 14 , wherein the layer of piezoelectric material directly contacts the drift zone region.
16 . The power transistor device of claim 14 , wherein the insulating structure further comprises at least one additional insulating layer.
17 . The power transistor device of claim 16 , wherein the at least one additional insulating layer is a SiO 2 layer.
18 . The power transistor device of claim 14 , wherein the field plate is electrically insulated from the transistor gate.
19 . The power transistor device of claim 18 , further comprising:
a body region in the semiconductor substrate; and
a source or emitter region in the semiconductor substrate above the body region, wherein the field plate is electrically connected to the source or emitter region.
20 . The power transistor device of claim 14 , wherein the field plate is electrically connected to the transistor gate.
21 . The power transistor device of claim 14 , wherein the layer of piezoelectric material comprises Al(Sc)N or BaTiO 3 or Pb (Zr,Ti)O 3 or doped ZrO 2 .
22 . The power transistor device of claim 14 , wherein the layer of piezoelectric material is configured to enhance the mobility of charge carriers in the drift zone region by introducing strain into the drift zone region that occurs in an ON state of the power transistor device as a result of the converse piezoelectric effect.
23 . The power transistor device of claim 22 , wherein the layer of piezoelectric material is configured such that in an OFF state of the power transistor device, the strain introduced into the drift zone region in the ON state of the power transistor device disappears.
24 . A power transistor device, comprising:
a semiconductor substrate;
a gate trench extending into the semiconductor substrate;
a transistor gate provided in the gate trench; and
an insulating structure formed between the transistor gate and a side wall of the gate trench, the insulating structure being configured to electrically insulate the transistor gate from a channel region which extends along the side wall of the gate trench, the insulating structure comprising a layer of piezoelectric material,
wherein the insulating structure further comprises a first insulating layer and a second insulating layer, the layer of piezoelectric material being sandwiched between the first insulating layer and the second insulating layer.
25 . The power transistor device of claim 24 , wherein the first insulating layer and/or the second insulating layer is a SiO 2 layer.
26 . A power transistor device, comprising:
a semiconductor substrate;
a gate trench extending into the semiconductor substrate;
a transistor gate provided in the gate trench;
an insulating structure formed between the transistor gate and a side wall of the gate trench, the insulating structure being configured to electrically insulate the transistor gate from a channel region which extends along the side wall of the gate trench, the insulating structure comprising a layer of piezoelectric material; and
a field plate provided in a field plate trench which is separate from the gate trench.