Method of forming a semiconductor device having gate spacers with regions of diffused silicon germanium
Some implementations described herein provide techniques and semiconductor devices in which a dielectric region is included in a nanostructure transistor. The dielectric region, which may correspond to an air gap, may be located between dielectric spacer layers located along a sidewall of a metal gate structure. Techniques to form the dielectric region may include using a temporary spacer layer between the dielectric spacer layers during manufacturing of the nanostructure transistor. The temporary spacer layer may include a silicon germanium material having a reaction mechanism that allows the temporary spacer layer to be selectively removed without causing damage to the dielectric spacer layers, the metal gate structure, or other portions of the nanostructure transistor.
1 . A method, comprising:
forming, over a semiconductor substrate, a plurality of nanostructure layers in a direction that is perpendicular to the semiconductor substrate, wherein the plurality of nanostructure layers comprises a plurality of sacrificial layers alternating with a plurality of channel layers;
forming, over the plurality of nanostructure layers, a dummy gate structure;
forming, along a sidewall of the dummy gate structure, a first spacer layer comprising a first nitride material;
forming, on the first spacer layer, a second spacer layer comprising a silicon germanium material;
forming, on the second spacer layer and on a top surface of a source drain region adjacent to the plurality of nanostructure layers, a third spacer layer comprising a second nitride material,
wherein a portion of at least one of the first spacer layer or the third spacer layer comprises a first region of diffused silicon germanium;
removing the dummy gate structure;
removing the plurality of sacrificial layers;
forming a metal gate structure,
wherein forming the metal gate structure comprises forming a first portion in place of the dummy gate structure and forming a second portion that wraps around a plurality of nanostructure channels formed from the plurality of channel layers; and
removing the second spacer layer to form, between the first spacer layer and the third spacer layer, a dielectric region,
wherein the dielectric region comprises air and resides on a top surface of the first spacer layer,
wherein the third spacer layer defines a sidewall of the dielectric region.
2 . The method of claim 1 ,
wherein forming the second spacer layer comprising the silicon germanium material comprises:
forming the second spacer layer using the silicon germanium material,
wherein a content of germanium in the silicon germanium material is in a range of approximately 10% to approximately 40%.
3 . The method of claim 1 ,
wherein removing the second spacer layer to form the dielectric region comprises:
etching the second spacer layer using a gaseous mixture comprising a hydrogen fluoride gas.
4 . The method of claim 1 ,
wherein removing the second spacer layer to form the dielectric region comprises:
etching the second spacer layer using a gaseous mixture comprising a fluorine gas.
5 . The method of claim 1 , further comprising:
forming, at an end of the dielectric region, a filler material between the first spacer layer and the third spacer layer.
6 . The method of claim 1 ,
wherein the dielectric region has a width that is in a range of approximately 1 nanometer to approximately 5 nanometers.
7 . A method, comprising:
forming, over a semiconductor substrate, a plurality of nanostructure layers in a direction that is perpendicular to the semiconductor substrate, wherein the plurality of nanostructure layers comprises a plurality of sacrificial layers alternating with a plurality of channel layers;
forming, over the plurality of nanostructure layers, a dummy gate structure;
forming, along a sidewall of the dummy gate structure, a first spacer layer comprising a first material;
forming, on the first spacer layer, a second spacer layer comprising a second material;
forming, on the second spacer layer and on a top surface of a source drain region adjacent to the plurality of nanostructure layers, a third spacer layer comprising a third material,
wherein a portion of at least one of the first spacer layer or the third spacer layer comprises a region of diffused silicon germanium;
removing the dummy gate structure;
removing the plurality of sacrificial layers;
forming a metal gate structure,
wherein forming the metal gate structure comprises forming a first portion in place of the dummy gate structure and forming a second portion that wraps around a plurality of nanostructure channels formed from the plurality of channel layers; and
removing the second spacer layer to form, between the first spacer layer and the third spacer layer, a dielectric region that resides on a top surface of the first spacer layer,
wherein removing the second spacer layer comprises using a gaseous mixture that has an accelerated reaction with the second material, relative to the first material and the third material, to perform an etch-selectivity operation that removes the second spacer layer from between the first spacer layer and the third spacer layer to form the dielectric region, and
wherein the third spacer layer defines a sidewall of the dielectric region.
8 . The method of claim 7 ,
wherein the accelerated reaction with the second material, relative to the first material, corresponds to a blanket film loss rate.
9 . The method of claim 7 , further comprising:
forming, at an end of the dielectric region, a hard masking layer between the first spacer layer and the third spacer layer to cap the dielectric region.
10 . A method, comprising:
forming, over a semiconductor substrate, a plurality of nanostructure layers comprising a plurality of sacrificial layers and a plurality of channel layers;
forming, over the plurality of nanostructure layers, a dummy gate structure;
forming, along a sidewall of the dummy gate structure, a plurality of spacer layers;
removing the dummy gate structure;
removing the plurality of sacrificial layers;
forming a metal gate structure,
wherein forming the metal gate structure comprises forming a first portion in place of the dummy gate structure and forming a second portion that wraps around a plurality of nanostructure channels formed from the plurality of channel layers; and
removing a first spacer layer, of the plurality of spacer layers, to form a dielectric region, and
wherein a portion of a second spacer layer, of the plurality of spacer layers, comprises a first region of diffused silicon germanium.
11 . The method of claim 10 ,
wherein the dielectric region comprises air.
12 . The method of claim 10 ,
wherein the first region of the diffused silicon germanium is at a depth that is in a range of approximately 1 nanometer to approximately 2 nanometers, wherein the depth is from a surface of the second spacer layer facing the dielectric region.
13 . The method of claim 10 ,
wherein the second spacer layer has a thickness that is in a range of approximately 1 nanometer to approximately 5 nanometers.
14 . The method of claim 10 ,
wherein a portion of a third spacer layer, of the plurality of spacer layers, comprises a second region of diffused silicon germanium.
15 . The method of claim 14 ,
wherein the second region of diffused silicon germanium is at a depth that is in a range of approximately 1 nanometer to approximately 2 nanometers, wherein the depth is from a surface of the third spacer layer facing the dielectric region.
16 . The method of claim 14 ,
wherein the first spacer layer is between the second spacer layer and the third spacer layer.
17 . The method of claim 14 , further comprising:
forming, at an end of the dielectric region, a filler material between the second spacer layer and the third spacer layer.
18 . The method of claim 10 ,
wherein removing the first spacer layer to form the dielectric region comprises:
etching the first spacer layer using a gaseous mixture comprising a hydrogen fluoride gas.
19 . The method of claim 10 ,
wherein removing the first spacer layer to form the dielectric region comprises:
etching the first spacer layer using a gaseous mixture comprising a fluorine gas.
20 . The method of claim 10 ,
wherein the dielectric region has a width that is in a range of approximately 1 nanometer to approximately 5 nanometers.