Siliciding method

1 . A method of manufacturing an integrated circuit, comprising:

providing a semiconductor wafer including first and second semiconductor regions, the first semiconductor region including a silicon-on-insulator structure having an insulating layer on top of and in contact with the semiconductor wafer and a silicon layer on top of and in contact with the insulating layer;

forming first and second transistors respectively within the first and second semiconductor regions;

wherein the first transistor has first source and first drain regions separated by a first channel-forming region, with the first source region, first drain region, and first channel-forming region being formed in the silicon layer,

the first source and first drain regions each including a portion of silicon epitaxially grown from the silicon layer such that the first source and first drain regions are raised with respect to a surface of the semiconductor wafer, the first channel-forming region being topped by a first gate stack, and first spacers covering sides of the first gate stack to separate and electrically insulate the first gate stack from the epitaxially grown portions of the first source and first drain regions;

wherein the second transistor has second source and second drain regions separated by a second channel-forming region, with the second source region, second drain region, and second channel-forming region being formed in the semiconductor wafer, the second channel-forming region being topped with a second gate stack, and second spacers covering sides of the second gate stack;

depositing a mask over the first and second semiconductor regions such that the mask covers the first and second transistors, and etching a portion of the mask covering the second semiconductor region to expose silicon regions to be silicided in the second semiconductor region;

performing a first siliciding in the second semiconductor region to form first silicided regions by:

depositing a first metal layer in the first and second semiconductor regions, with the first metal layer in the first semiconductor region being deposited to directly contact the mask and, in the second semiconductor region, being deposited in openings formed in the mask by etching to directly contact the second gate stack, second spacers, and second source and second drain regions of the second transistor; and

performing a first annealing so that the first metal layer reacts with silicon in the second semiconductor region that the first metal layer is in contact with to form the first silicided regions atop the second source and second drain regions of the second transistor as well as to form the first silicided region atop the second gate stack of the second transistor;

removing the first metal layer and the mask to expose in the first semiconductor region, regions atop the first source and first drain regions of the first transistor as well as a region atop the first gate stack of the first transistor;

performing an implantation on the first silicided regions within the second semiconductor region and the regions to be silicided in the first semiconductor region, the implantation within the first semiconductor region being into the epitaxially grown portions of the first source and first drain regions of the first transistor;

wherein the implantation is amorphizing and breaks a crystal structure of silicon in the second semiconductor region across a given thickness thereof extending from an exposed surface of the second semiconductor region down to a given depth, wherein the given thickness is less than a total thickness of the second semiconductor region;

performing a second siliciding in the first semiconductor region to form second silicided regions by:

depositing a second metal layer over the first and second semiconductor regions; and

performing a second annealing so that the second metal layer reacts with silicon in the first semiconductor region that the second metal layer is in contact with to thereby form the second silicided regions atop the epitaxially grown portions of the first source and first drain regions of the first transistor as well as form the second silicided region atop the first gate stack of the first transistor;

removing the second metal layer to remove unreacted portions thereof, and

performing a third annealing to favor, in the second semiconductor region, accumulation of atoms implanted, during the implantation on the first silicided region within the second semiconductor region, at an interface between the first silicided region and the silicon on which they rest.

2 . The method of claim 1 , wherein a width of the second spacers is greater than a width of the first spacers.

3 . The method of claim 1 , wherein the silicon-on-insulator structure results in the first transistor operating in a fully depleted mode such that the silicon layer and insulating layer form a fully-depleted silicon-on-insulator structure.

4 . The method of claim 1 , further comprising forming an insulating wall in the semiconductor wafer to separate and insulate the first and second transistors from one another.

5 . The method of claim 1 , wherein the second annealing is shorter and carried out at a lower temperature than the first annealing so that the second annealing does not modify thickness and composition of the first silicided regions formed during the first annealing.

6 . The method of claim 5 , wherein the third annealing is longer than the second annealing but shorter than the first annealing and is carried out a temperature higher than the first and second annealings.

7 . The method of claim 1 , wherein the removal of the first metal layer is performed by wet etching; and wherein the removal of the second metal layer is performed by wet etching.

8 . The method of claim 1 , wherein the first transistor is a low-voltage transistor and the second transistor is a high-voltage transistor.

9 . The method of claim 1 , wherein, as a result of the implantation being performed within the first semiconductor region into the epitaxially grown portions of the first source and first drain regions of the first transistor, PN junctions of the first transistor are not modified by the implantation due to a distance between the PN junctions of the first transistor and the epitaxially grown portions of the first source and first drain regions of the first transistor.