IP Library Granted Patent US 12707707
Granted Patent B2
US 12707707 · App. 18/463,138 · Granted Aug 11, 2026

Semiconductor device

Inventors: Kazutoshi Nakamura (Nonoichi Ishikawa, JP); Shunta Murai (Kanazawa Ishikawa, JP); Daiki Yoshikawa (Kanazawa Ishikawa, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H10D84/617H10D8/422H10D12/481H10D62/127
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Quick Facts
Patent No.
US 12707707
App. No.
18/463,138
Filed
Sep 7, 2023
Granted
Aug 11, 2026
Kind
B2
Examiner
ERDEM, FAZLI
Art Unit
2812
USPC
257/140
Abstract

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first region, and a second region. The second electrode is separated from the first electrode. The first region includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a sixth semiconductor region of the first conductivity type. The fifth semiconductor region, located between the fourth semiconductor region and a portion of the third semiconductor region, has a higher first-conductivity-type impurity concentration than the third semiconductor region. The sixth semiconductor region, located between the third semiconductor region and the portion of the second electrode, has a higher first-conductivity-type impurity concentration than the third semiconductor region.

Claims (64)

1 . A semiconductor device, comprising:

a first electrode;

a second electrode separated from the first electrode;

a first region located on a portion of the first electrode and positioned between the first electrode and the second electrode, the first region including

a first semiconductor region of a first conductivity type,

a second semiconductor region of a second conductivity type, a portion of the second semiconductor region being located on the first semiconductor region,

a third semiconductor region located on the portion of the second semiconductor region, the third semiconductor region being of the first conductivity type,

a gate electrode facing the third semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction, the first direction being from the first electrode toward the second electrode,

a fourth semiconductor region located on the third semiconductor region and arranged with a portion of the second electrode in the second direction, the fourth semiconductor region being of the second conductivity type,

a fifth semiconductor region located between the fourth semiconductor region and a portion of the third semiconductor region in a third direction, the fifth semiconductor region being of the first conductivity type, the third direction being perpendicular to the first and second directions, the fifth semiconductor region being arranged with the portion of the second electrode in the second direction, a first-conductivity-type impurity concentration of the fifth semiconductor region being greater than a first-conductivity-type impurity concentration of the third semiconductor region, and

a sixth semiconductor region located between the third semiconductor region and the portion of the second electrode, the sixth semiconductor region being of the first conductivity type, a first-conductivity-type impurity concentration of the sixth semiconductor region being greater than the first-conductivity-type impurity concentration of the third semiconductor region; and

a second region located on an other portion of the first electrode and positioned between the first electrode and the second electrode, the second region including

a seventh semiconductor region of the second conductivity type, the seventh semiconductor region having a higher second-conductivity-type impurity concentration than the second semiconductor region,

an other portion of the second semiconductor region located on the seventh semiconductor region, and

an eighth semiconductor region located on the other portion of the second semiconductor region, the eighth semiconductor region being of the first conductivity type.

2 . The device according to claim 1 , wherein

the fourth semiconductor region is located between a pair of the fifth semiconductor regions in the third direction.

3 . The device according to claim 2 , wherein

the portion of the third semiconductor region is alternately arranged in the third direction with a group including the fourth semiconductor region and the pair of fifth semiconductor regions.

4 . The device according to claim 1 , wherein

the first region includes a first part, and a second part positioned between the first part and the second region,

the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region each are located in the first part and in the second part, and

a length in the third direction of the fifth semiconductor region located in the first part is greater than a length in the third direction of the fifth semiconductor region located in the second part.

5 . The device according to claim 4 , wherein

a plurality of the fifth semiconductor regions is arranged in the second direction in the second part, and

lengths in the third direction of the plurality of fifth semiconductor regions decrease toward the second region.

6 . The device according to claim 4 , wherein

a length in the second direction of the second part is greater than a distance in the first direction between the first electrode and the second electrode.

7 . The device according to claim 1 , wherein

a first-conductivity-type impurity concentration of the eighth semiconductor region is less than a first-conductivity-type impurity concentration of the third semiconductor region.

8 . The device according to claim 1 , wherein the fourth semiconductor region directly contacts both the portion of the second electrode and the gate insulating layer.

9 . The device according to claim 1 , wherein the fifth semiconductor region directly contacts both the portion of the second electrode and the gate insulating layer.

10 . The device according to claim 1 , wherein the fourth semiconductor region directly contacts the fifth semiconductor region in the third direction.

11 . The device according to claim 1 , wherein the third semiconductor region directly contacts the fifth semiconductor region in the third direction.

12 . The device according to claim 2 , wherein

the fifth semiconductor region is located between a pair of the fourth semiconductor regions in the third direction, and

the fifth semiconductor region directly contacts both of the pair of the fourth semiconductor regions.

13 . A semiconductor device, comprising:

a first electrode;

a second electrode separated from the first electrode;

a first region located on a portion of the first electrode and positioned between the first electrode and the second electrode, the first region including

a first semiconductor region located in a first part of the first region and in a second part of the first region, the first semiconductor region being of a first conductivity type,

a second semiconductor region of a second conductivity type, a portion of the second semiconductor region being located on the first semiconductor region,

a third semiconductor region located in the first and second parts and positioned on the portion of the second semiconductor region, the third semiconductor region being of the first conductivity type,

a gate electrode located in the first part, the gate electrode facing the third semiconductor region via a gate insulating layer in a second direction perpendicular to a first direction, the first direction being from the first electrode toward the second electrode,

a fourth semiconductor region located in the first part and in the second part, the fourth semiconductor region being of the second conductivity type, the fourth semiconductor region being positioned on the third semiconductor region and arranged with a portion of the second electrode in the second direction,

a fifth semiconductor region located in the first part, the fifth semiconductor region being of the first conductivity type, the fifth semiconductor region being arranged with the portion of the second electrode in the second direction, a first-conductivity-type impurity concentration of the fifth semiconductor region being greater than a first-conductivity-type impurity concentration of the third semiconductor region, and

a sixth semiconductor region located in the first part and in the second part, the sixth semiconductor region being of the first conductivity type, the sixth semiconductor region being positioned between the third semiconductor region and the portion of the second electrode, a first-conductivity-type impurity concentration of the sixth semiconductor region being greater than the first-conductivity-type impurity concentration of the third semiconductor region, the fourth semiconductor region and the fifth semiconductor region being alternately arranged in a third direction in the first part, the fourth semiconductor region and a portion of the third semiconductor region being alternately arranged in the third direction in the second part, the third direction being perpendicular to the first and second directions; and

a second region located on an other portion of the first electrode and positioned between the first electrode and the second electrode, the second region including

a seventh semiconductor region of the second conductivity type, the seventh semiconductor region having a higher second-conductivity-type impurity concentration than the second semiconductor region,

an other portion of the second semiconductor region located on the seventh semiconductor region,

an eighth semiconductor region located on the other portion of the second semiconductor region, the eighth semiconductor region being of the first conductivity type,

the second part being positioned between the first part and the second region.

14 . The device according to claim 13 , wherein

a length in the second direction of the second part is greater than a distance between the first electrode and the second electrode.

15 . The device according to claim 13 , wherein

a plurality of the sixth semiconductor regions is arranged in the third direction in the second part, and

the plurality of sixth semiconductor regions is separated from each other.

16 . The device according to claim 13 , wherein

a first-conductivity-type impurity concentration of the eighth semiconductor region is less than a first-conductivity-type impurity concentration of the third semiconductor region.

17 . The device according to claim 13 , wherein the fourth semiconductor region directly contacts both the portion of the second electrode and the gate insulating layer.

18 . The device according to claim 13 , wherein the fifth semiconductor region directly contacts both the portion of the second electrode and the gate insulating layer.

19 . The device according to claim 13 , wherein the fourth semiconductor region located in the first part directly contacts the fifth semiconductor region in the third direction (Y).

20 . The device according to claim 13 , wherein the fourth semiconductor region located in the second part directly contacts the third semiconductor region in the third direction.