Semiconductor structure and method for forming same
View Patent ↗Semiconductor structures and methods for forming the same are provided. In one form, a semiconductor structure includes: a substrate; a first dielectric layer, located on the substrate; a trench, located in the first dielectric layer; a conductive layer, located on a bottom and a sidewall of the trench and configured as a resistor structure; and a second dielectric layer, configured to be filled in the trench where the conductive layer is formed. By means of embodiments and implementations of the present disclosure, an equivalent conductive sectional area of the resistor structure is increased, and a transverse area occupied by the resistor structure is reduced, thereby miniaturizing the device.
1 . A semiconductor structure, comprising:
a substrate comprising a device region configured to form a transistor and a resistor region configured to form the resistor structure;
a first dielectric layer, located on the substrate;
a trench, located in the first dielectric layer;
a conductive layer, located on a bottom and a sidewall of the trench and configured as a resistor structure;
a second dielectric layer, configured to be filled in the trench where the conductive layer is formed;
a channel structure, located on the substrate of the device region;
an isolation layer, located on the substrate and surrounding the channel structure; and
an interlayer dielectric layer, located on the isolation layer, wherein the interlayer dielectric layer and the isolation layer are configured as a first dielectric layer.
2 . The semiconductor structure according to claim 1 , wherein:
the semiconductor structure further comprises:
the trench extends through the interlayer dielectric layer of the resistor region.
3 . The semiconductor structure according to claim 2 , wherein:
the semiconductor structure further comprises: a contact etch stop layer, located between the isolation layer and the interlayer dielectric layer, and the contact etch stop layer is exposed from the bottom of the trench.
4 . The semiconductor structure according to claim 2 , further comprising:
a gate structure, located on the isolation layer of the device region and spanning the channel structure;
a source/drain doped region, located on two sides of the gate structure and in contact with end portions of the channel structure along an extending direction; and
a source/drain interconnect layer, extending through the interlayer dielectric layer on a top of the source/drain doped region and in contact with the source/drain doped region.
5 . The semiconductor structure according to claim 2 , wherein:
the trench is located in the interlayer dielectric layer of the resistor region and the isolation layer is exposed from the trench; and
the semiconductor structure further comprises: a spacer, located on a sidewall of the gate structure and between a sidewall of the conductive layer and the interlayer dielectric layer.
6 . The semiconductor structure according to claim 5 , further comprising: a contact etch stop layer, located between the isolation layer and the interlayer dielectric layer and between the spacer and the interlayer dielectric layer.
7 . The semiconductor structure according to claim 1 , wherein a material of the conductive layer comprises at least one of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, or Ni.