Amorphized subfins using backside implantation
Techniques to form semiconductor devices that include subfins that are at least partially amorphized are described. A backside dopant implantation process using dopants (e.g., germanium) may be used to create amorphous semiconductor material in the subfins. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region formed from a fin of semiconductor material. The fin includes a subfin laterally adjacent to a dielectric fill. A backside ion implantation process may be used to implant dopants such as Ge into the subfin and consequently form an amorphized portion of the subfin. In some examples, the amorphized portion is under the gate structure and laterally between a source region and a drain region. The amorphized portion may extend from a bottom surface of the subfin to just under the gate structure, and in some cases, leave a crystalline portion of subfin below the gate structure.
1 . An integrated circuit comprising:
a semiconductor region extending from a source or drain region in a first direction;
a gate structure extending over the semiconductor region in a second direction different from the first direction;
a subfin directly beneath the semiconductor region, wherein a first portion of the subfin that is laterally adjacent to the source or drain region comprises amorphized semiconductor material, and a second portion of the subfin that is laterally adjacent to the source or drain region comprises crystallized semiconductor material, the second portion being directly on the first portion; and
a dielectric layer adjacent to the subfin and beneath the gate structure.
2 . The integrated circuit of claim 1 , wherein the dielectric layer is a first dielectric layer and the integrated circuit further comprises one or more conductive layers on a bottom surface of a second dielectric layer, such that the second dielectric layer is between the one or more conductive layers and the first dielectric layer.
3 . The integrated circuit of claim 1 , wherein the gate structure comprises a gate electrode and a gate dielectric, and wherein the gate dielectric is on the subfin.
4 . The integrated circuit of claim 1 , wherein the second portion of the subfin is between the first portion of the subfin and the semiconductor region.
5 . The integrated circuit of claim 1 , wherein the amorphized semiconductor material comprises silicon and germanium.
6 . The integrated circuit of claim 1 , wherein a printed circuit board comprises the integrated circuit of claim 1 .
7 . An electronic device, comprising:
a chip package comprising one or more dies, at least one of the one or more dies comprising
a semiconductor device having a semiconductor region extending in a first direction from a source or drain region, and a gate structure extending over the semiconductor region in a second direction different from the first direction;
a subfin directly beneath the semiconductor region, wherein a first portion of the subfin that is laterally adjacent to the source or drain region and under the gate structure comprises amorphized silicon, and a second portion of the subfin that is laterally adjacent to the source or drain region and under the gate structure comprises crystallized semiconductor material, the second portion being directly on the first portion; and
a dielectric layer laterally adjacent to the subfin.
8 . The electronic device of claim 7 , wherein the gate structure comprises a gate electrode and a gate dielectric, and wherein the gate dielectric is on the subfin.
9 . The electronic device of claim 7 , wherein the second portion of the subfin is between the first portion of the subfin and the semiconductor region.
10 . The electronic device of claim 7 , wherein the first portion of the subfin comprises germanium.
11 . The electronic device of claim 7 , further comprising a printed circuit board, wherein the chip package is attached to the printed circuit board.
12 . An integrated circuit comprising:
a subfin of a semiconductor device, the subfin being beneath a semiconductor region and laterally adjacent to a dielectric layer, wherein a first portion of the subfin comprises amorphized silicon, and a second portion of the subfin comprises crystallized semiconductor material, the second portion being directly on the first portion; and
a gate structure over the semiconductor region such that the subfin is beneath the gate structure.
13 . The integrated circuit of claim 12 , wherein the dielectric layer is a first dielectric layer and the integrated circuit further comprises one or more conductive layers on a bottom surface of a second dielectric layer, such that the second dielectric layer is between the one or more conductive layers and the first dielectric layer.
14 . The integrated circuit of claim 12 , wherein the gate structure comprises a gate electrode and a gate dielectric, and wherein the gate dielectric is on the subfin.
15 . The integrated circuit of claim 12 , wherein the second portion of the subfin is laterally between a source region and a drain region.
16 . The integrated circuit of claim 12 , wherein the second portion of the subfin is between the first portion of the subfin and the semiconductor region.
17 . The integrated circuit of claim 12 , wherein the first portion of the subfin comprises germanium.
18 . The integrated circuit of claim 12 , wherein a printed circuit board comprises the integrated circuit.
19 . The integrated circuit of claim 1 , wherein the first portion of the subfin extends through at least 90% of a total thickness of the subfin.
20 . The integrated circuit of claim 12 , wherein the first portion of the subfin extends through at least 90% of a total thickness of the subfin.